Nokia 3105 Servicehandbuch
CCS Technical Documentation
Troubleshooting — BB
RH-48
Issue 1 11/2003
© 2003 Nokia Corporation Confidential
Page 11
Clock Distribution
RFClk (19.2 MHz Analog)
The main clock signal for the baseband is generated from the voltage and temperature
controlled crystal oscillator VCTCXO (G500). This 19.2 MHz clock signal is generated at
the RF and is fed to Yoda pin 18 (TCXO_IN). Yoda then converts the analog sine wave-
form to a digital waveform with swing voltage of 0 tot 1.8V and sends it to the UPP
from pin 16 at Yoda (19.2 Out) to the UPP pin M5 (RFCLK). (See Figure 4 for waveform.)
controlled crystal oscillator VCTCXO (G500). This 19.2 MHz clock signal is generated at
the RF and is fed to Yoda pin 18 (TCXO_IN). Yoda then converts the analog sine wave-
form to a digital waveform with swing voltage of 0 tot 1.8V and sends it to the UPP
from pin 16 at Yoda (19.2 Out) to the UPP pin M5 (RFCLK). (See Figure 4 for waveform.)
Figure 4: Waveform of 19.2MHz clock (VCTCXO) going to the Yoda ASIC