Fujifilm Xeon S26361-F3099-L828 Datenbogen
Produktcode
S26361-F3099-L828
Datasheet
15
2.3.2
Phase Lock Loop (PLL) and Filter
V
CCA
and V
CCIOPLL
are power sources required by the PLL clock generators on the Low Voltage
Intel
®
Xeon™ processor with 800 MHz system bus. Since these PLLs are analog in nature, they
require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades
external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this
degradation, these supplies must be low pass filtered from V
external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this
degradation, these supplies must be low pass filtered from V
TT
.
The AC low-pass requirements are as follows:
•
< 0.2 dB gain in pass band
•
< 0.5 dB attenuation in pass band < 1 Hz
•
> 34 dB attenuation from 1 MHz to 66 MHz
•
> 28 dB attenuation from 66 MHz to core frequency
.
NOTES:
1. Diagram not to scale.
2. No specifications for frequencies beyond f
2. No specifications for frequencies beyond f
core
(core frequency).
3. f
peak
, if existent, should be less than 0.05 MHz.
4. f
core
represents the maximum core frequency supported by the platform.
Table 3.
BSEL[1:0] Frequency Table
BSEL1
BSEL0
Bus Clock Frequency
0
0
Reserved
0
1
Reserved
1
0
200 MHz
1
1
Reserved
Figure 1.
Phase Lock Loop (PLL) Filter Requirements
CS00141
0.2 dB
0 dB
x dB
–28 dB
–34 dB
66 MHz
1.67 GHz
1 MHz
1 Hz
DC
fpeak
fcore
Passband
High
Frequency
<50 kHz
500 MHz