Intel E3815 FH8065301567411 Datenbogen
Produktcode
FH8065301567411
Electrical Specifications
Intel
®
Atom™ Processor E3800 Product Family
150
Datasheet
9.6.5
DDR3L Memory Controller AC Specification
Note:
The contents of this section are only valid for
DRAM_VDD_S4
= 1.35V
Figure 20. SVID Timing Diagram
Table 110. DDR3L Interface Timing Specification (Sheet 1 of 3)
Symbol
Parameter
Min
Max
Unit
Figure
Notes
DDR3L Electrical Characteristic and AC timings at 1066 MT/s
T
SLR_D
DQ, DQSP, DQSN Input Slew Rate
3
5.5
V/ns
System Memory Clock Timings
T
CK(AVG)
Average CK Period
1.875
ns
T
CH
Average CK High Time
0.45
tCKAV
G
T
CL
Average CK Low Time
0.45
tCKAV
G
T
SKEW
Skew between any System Memory
Differential Clock Pair (CKP/CKN)
Differential Clock Pair (CKP/CKN)
30
ps
System Memory Command Signal Timings
T
CMD
(tCMDVB+tCMDVA)
Total CMD Buffer window available for
command buffers (RAS#, CAS#,
WE#, BS[2:0], MA)
command buffers (RAS#, CAS#,
WE#, BS[2:0], MA)
1380
ps
1
System Memory Control Signal Timings
SVID_CLK
T
SVID
T
DC
T
DC
SVID_DATA
Output (WRITE)
T
S-D
T
H-D
SVID_DATA
Input (READ)
0.5*VDD
0.5*VDD
0.5*VDD
0.5*VDD
T
CO_D Min
T
CO_D Max