Intel E3815 FH8065301567411 Datenbogen

Produktcode
FH8065301567411
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Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
2375
23:16
08h
RW
Interrupt Threshold Control (ITC_0): This field is used by system 
software to select the maximum rate at which the host controller will issue 
interrupts. The only valid values are defined below. If software writes an 
invalid value to this register, the results are undefined. Value Maximum 
Interrupt Interval 00h Reserved 01h 1 micro-frame 02h 2 micro-frames 04h 
4 micro-frames 08h 8 micro-frames (default, equates to 1 ms) 10h 16 micro-
frames (2 ms) 20h 32 micro-frames (4 ms) 40h 64 micro-frames (8 ms) 
Refer to Section 4 in the EHCI specification for interrupts affected by this 
field.
Power Well: Core
15:14
00b
RO
Reserved (RSVD): Reserved.
13
0b
RO
Reserved (RSVD): Reserved.
12
0h
RO
Reserved (RSVD): Reserved.
11:8
0h
RO
Unimplemented Asynchronous Park Mode Bits (UAPMB_0): This field 
is hardwired to 000b because the host controller does not support this 
optional feature.
Power Well: Core
7
0b
RO
Light Host Controller Reset (LHCR_0): Read Only 0b. The Intel EHC does 
not implement this optional reset and hardwires this bit to 0.
Power Well: Core
6
0b
RW
Interrupt on Async Advance Doorbell (IAAD_0): This bit is used as a 
doorbell by software to tell the host controller to issue an interrupt the next 
time it advances asynchronous schedule. Software must write a 1 to this bit 
to ring the doorbell. When the host controller has evicted all appropriate 
cached schedule state , it sets the Interrupt on Async Advance status bit in 
the USBSTS register. If the Interrupt on Async Advance Enable bit in the 
USBINTR register is a one then the host controller will assert an interrupt at 
the next interrupt threshold. See the EHCI specification for operational 
details. The host controller sets this bit to a zero after it has set the Interrupt 
on Async Advance status bit in the USBSTS register to a one. Software 
should not write a one to this bit when the asynchronous schedule is 
disabled. Doing so will yield undefined results.
Power Well: Core
5
0b
RW
Asynchronous Schedule Enable (ASE_0): This bit controls whether the 
host controller skips processing the Asynchronous Schedule. Values mean: 
0b Do not process the Asynchronous Schedule 1b Use the ASYNCLISTADDR 
register to access the Asynchronous Schedule.
Power Well: Core
Bit 
Range
Default 
& Access
Field Name (ID): Description