Intel E3815 FH8065301567411 Datenbogen

Intel

®

 Atom™ Processor E3800 Product Family

296

Datasheet

DRAM Reset Management Control

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0

MRRDA

TA

T

Q

POLLPER

T

Q

POLLE

N

Rsvd_19_DCAL

TQ

POLLRS

T

Q

POLLS

TR

T

ZQ

CA

LSTR

T

ZQ

CA

LT

Y

PE

SRXZQ

CL

Rsvd_11_DCAL

ZQ

CINT

Rsvd_

7_0_DCAL

31:24

0h

RO

MRR Data This field contains the data of the last DRAM Mode Register Read 

(MRR) issued thru message opcode 68h or from a TQ Poll. It is over-written with each 

MRR command. Note: This is an LPDDR feature only.

23:21

0h

RW/P

TQ Poll Period 0h - 1 x the current Refresh Period 1h - 2 x the current 

Refresh Period 2h - 4 x the current Refresh Period 3h - 8 x the current Refresh Period 4h 

- 16 x the current Refresh Period 5h - 32 x the current Refresh Period 6h - 64 x the 

current Refresh Period 7h - 128 x the current Refresh Period Note: This is an LPDDR 

feature only.

20

0h

RW/P

TQ Poll Enable 0 - Disables periodic TQ polling 1 - Enables periodic TQ 

polling Note: This is an LPDDR feature only.

19

0h

RO

Reserved

18:17

0h

RW/P

TQ Poll RS This bit selects which rank to poll the LPDDR2 DRAMs internal 

MR4 register. The assumption is that the temperature will be similar for any rank, and 

thus polling only a single memory device in the package is sufficient. 00 - Select Rank 0 

to poll from 01 - Select Rank 1 to poll from 10 - Select Rank 2 to poll from 11 - Select 

Rank 3 to poll from Note: This is an LPDDR feature only.

16

0h

RW/P

TQ Poll Start Set this bit to 1 to start a TQPoll. This bit will remain a 1 

until the TQPoll process is complete, then it will return to 0. 0 - TQ Poll is done 1 - TQ 

Poll has started and is in progress Note: This is an LPDDR feature only.

15

0h

RW/P

ZQ Calibration Start Set this bit to 1 to start the ZQ calibration sequence. 

This bit will remain a 1 until the ZQ calibration is complete, then it will return to 0. 0 - 

ZQ calibration is done 1 - ZQ calibration has started and is in progress

14

0h

RW/P

ZQ Calibration Type 0 - Short Calibration 1 - Long Calibration

13:12

1h

RW/P

ZQ Calibration Long After SR Exit Control 0h - ZQCL commands after SRX 

are sent in parallel. 1h - ZQCL commands are sent serially to ranks (not used). 2h - No 

ZQCL is sent after SR Exit (for Debug only). 3h Reserved.

11

0h

RO

Reserved

10:8

3h

RW/P

ZQ Calibration Short Interval. The time interval, in ms, between ZQCS 

commands to a DRAM device. ZQCS commands are sent to a single DRAM device and 

commands are distributed and non-overlapping in the interval. 0h - Disabled 1h - 62s 

(for pre-silicon simulation only) 2h - 31ms 3h - 63ms 4h - 126ms Others - Reserved 

May be changed on-the-fly in response to thermal events.

7:0

0h

RO

Reserved