Fujitsu MB91191 Benutzerhandbuch
198
CHAPTER 10 Timer
[bit1]:TCS10
It is clock source selection bit of timer.
[bit0]:TSTR1
It is timer start bit.
■
Timer Control Register 0 (TxCR0)
Figure 10.6-2 Timer control register 0 (TxCR0)
[bit7]:TIF0
It is compare match detection flag bit.
[bit6]:TFCR0
It is compare match detection flag clear bit.
The read value of this bit is always "1".
TCS12 TCS11 TCS10 Selection
Clock
source
in fch = @20 MHz
0 0 0 2
4
/fch (FRC3)
0.8
µs
0 0 1 2
6
/fch (FRC5)
3.2
µs
0 1 0 2
8
/fch (FRC7)
12.8
µs
0 1 1
Setting disabled
1 0 0
1 0 1
1 1 0
1 1 1 16-bit
mode
-
0 Operation
stop
1
Clear counter and start operation.
7 6 5 4 3 2 1 0
0100 0000
B
Initial value
bit
R
W
R/W
R/W
R/W
R/W
R/W
TIF0
TFCR0
TIE0
TCS02
TCS01
TCS00
TSTR0
CINV
R/W
Access
0
Compare match does not generate.
1
Compare match generates.
0
Clear compare match detection flag.
1 None