Intel 8XC196MH Benutzerhandbuch
14-5
SPECIAL OPERATING MODES
The device enters idle mode after executing the IDLPD #1 instruction. Any enabled interrupt
source, either internal or external, or a hardware reset can cause the device to exit idle mode.
When an interrupt occurs, the CPU clocks restart and the CPU executes the corresponding inter-
rupt service or PTS routine. When the routine is complete, the CPU fetches and then executes the
instruction that follows the IDLPD #1 instruction.
source, either internal or external, or a hardware reset can cause the device to exit idle mode.
When an interrupt occurs, the CPU clocks restart and the CPU executes the corresponding inter-
rupt service or PTS routine. When the routine is complete, the CPU fetches and then executes the
instruction that follows the IDLPD #1 instruction.
NOTE
If enabled, the watchdog timer continues to run in idle mode. The device must
be awakened before the counter overflows; otherwise, the timer will reset the
device. The watchdog timer interval is always 64K state times in the
8XC196MC and MD, but a longer interval can be selected in the 8XC196MH
(see “Enabling the Watchdog Timer” on page 13-12).
be awakened before the counter overflows; otherwise, the timer will reset the
device. The watchdog timer interval is always 64K state times in the
8XC196MC and MD, but a longer interval can be selected in the 8XC196MH
(see “Enabling the Watchdog Timer” on page 13-12).
To prevent an accidental return to full power, hold the external interrupt pin
(EXTINT) low while the device is in idle mode.
(EXTINT) low while the device is in idle mode.
14.4 POWERDOWN MODE
Powerdown mode places the device into a very low power state by disabling the internal oscilla-
tor and clock generators. Internal logic holds the CPU and peripheral clocks at logic zero, which
causes the CPU to stop executing instructions, the system bus-control signals to become inactive,
the CLKOUT signal to become high, and the peripherals to turn off. Power consumption drops
into the microwatt range (refer to the datasheet for exact specifications). I
tor and clock generators. Internal logic holds the CPU and peripheral clocks at logic zero, which
causes the CPU to stop executing instructions, the system bus-control signals to become inactive,
the CLKOUT signal to become high, and the peripherals to turn off. Power consumption drops
into the microwatt range (refer to the datasheet for exact specifications). I
CC
is reduced to device
leakage. Tables in Appendix B list the values of the pins during powerdown mode (see Table B-8
on page B-23 for the 8XC196MC and 8XC196MD or Table B-9 on page B-25 for the
8XC196MH). If V
on page B-23 for the 8XC196MC and 8XC196MD or Table B-9 on page B-25 for the
8XC196MH). If V
CC
is maintained above the minimum specification, the special-function regis-
ters (SFRs) and register RAM retain their data.
14.4.1 Enabling and Disabling Powerdown Mode
The PD bit in the chip configuration register 0 (CCR0.0) either enables or disables powerdown
mode. Because CCR0 cannot be accessed by code, the PD bit value is defined in chip configura-
tion byte 0 (CCB0.0). Setting the PD bit enables powerdown mode and clearing it disables pow-
erdown. CCR0 is loaded from CCB0 when the device returns from reset. Refer to “Operating
Environment” on page 16-17 for descriptions of the methods for programming the CCBs.
mode. Because CCR0 cannot be accessed by code, the PD bit value is defined in chip configura-
tion byte 0 (CCB0.0). Setting the PD bit enables powerdown mode and clearing it disables pow-
erdown. CCR0 is loaded from CCB0 when the device returns from reset. Refer to “Operating
Environment” on page 16-17 for descriptions of the methods for programming the CCBs.