Benutzerhandbuch für Philips P89LPC902

Inhaltsverzeichnis

• 1. General Description

  7
• Pin Configurations

  7
• Product comparison

  8
• Pin Descriptions - P89LPC901

  12
• Pin Descriptions - P89LPC902

  14
• Pin Descriptions - P89LPC903

  15
• Special Function Registers

  16
• Special Function Registers Table - P89LPC901

  16
• Special Function Registers Table - P89LPC902

  19
• Special Function Registers Table - P89LPC903

  22
• Memory Organization

  25
• 2. Clocks

  27
• Enhanced CPU

  27
• Clock Definitions

  27
• CPU Clock (OSCCLK)

  27
• Low Speed Oscillator Option - P89LPC901

  27
• Medium Speed Oscillator Option - P89LPC901

  27
• High Speed Oscillator Option - P89LPC901

  27
• Oscillator Option Selection- P89LPC901

  28
• Clock Output - P89LPC901

  28
• On-Chip RC oscillator Option

  28
• Watchdog Oscillator Option

  29
• External Clock Input Option - P89LPC901

  29
• CPU Clock (CCLK) Wakeup Delay

  32
• CPU Clock (CCLK) Modification: DIVM Register

  32
• Low Power Select (P89LPC901)

  33
• 3. Interrupts

  35
• Interrupt Priority Structure

  35
• External Interrupt Inputs

  37
• External Interrupt Pin Glitch Suppression

  37
• 4. I/O Ports

  39
• Port Configurations

  39
• Quasi-Bidirectional Output Configuration

  39
• Open Drain Output Configuration

  40
• Input-Only Configuration

  41
• Push-Pull Output Configuration

  41
• Port 0 Analog Functions

  41
• Additional Port Features

  42
• 5. Timers 0 and 1

  45
• Mode 0

  46
• Mode 2

  46
• Mode 3

  47
• Mode 6 - P89LPC901

  47
• Timer Overflow toggle output - P89LPC901

  49
• 6. Real-Time Clock/System Timer

  51
• Real-time Clock Source

  51
• Changing RTCS1-0

  53
• Real-time Clock Interrupt/Wake Up

  53
• Reset Sources Affecting the Real-time Clock

  53
• 7. Power Monitoring Functions

  55
• Brownout Detection

  55
• Power-On Detection

  56
• Power Reduction Modes

  57
• 8. UART (P89LPC903)

  61
• Mode 0

  61
• Mode 1

  61
• Mode 2

  61
• Mode 3

  61
• SFR Space

  62
• Baud Rate Generator and Selection

  62
• Updating the BRGR1 and BRGR0 SFRs

  62
• Framing Error

  63
• Break Detect

  63
• More About UART Mode 0

  65
• More About UART Mode 1

  66
• More About UART Modes 2 and 3

  67
• Framing Error and RI in Modes 2 and 3 with SM2 = 1

  67
• Break Detect

  67
• Double Buffering

  68
• Double Buffering in Different Modes

  68
• The 9th Bit (Bit 8) in Double Buffering (Modes 1, 2 and 3)

  69
• Multiprocessor Communications

  70
• Automatic Address Recognition

  70
• 9. Reset

  73
• Power-On reset code execution

  73
• 10. Analog Comparators

  75
• Comparator Configuration

  75
• Internal Reference Voltage

  77
• Comparator Interrupt

  77
• Comparator and Power Reduction Modes

  78
• Comparator Configuration Example

  78
• 11. Keypad Interrupt (KBI)

  79
• 12. Watchdog Timer

  83
• Watchdog Function

  83
• Feed Sequence

  84
• Watchdog Timer in Timer Mode

  87
• Power down operation

  87
• Watchdog Clock Source

  87
• Periodic wakeup from Power down without an external oscillator

  89
• 13. Additional Features

  91
• Software Reset

  91
• Dual Data Pointers

  91
• 14. Flash program memory

  93
• General description

  93
• Features

  93
• Introduction to IAP-Lite

  93
• Using Flash as data storage

  93
• Accessing additional flash elements

  96
• Erase-programming additional flash elements

  97
• Reading additional flash elements

  97
• User Configuration Bytes

  99
• User Security Bytes

  101
• Boot Vector

  102
• Boot Status

  102
• 15. Instruction set

  103
• 16. Revision History

  107
• 17. Index

  109