BenutzerhandbuchInhaltsverzeichnisNOTIFICATION OF REVISIONS3Table of Contents8List of Figures13List of Tables17List of Programming Tips19List of Register Descriptions20List of Instruction Descriptions211 PRODUCT OVERVIEW23S3C8-SERIES MICROCONTROLLERS23S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER23FLASH23FEATURES24BLOCK DIAGRAM25PIN ASSIGNMENT26PIN DESCRIPTIONS28PIN CIRCUITS30Figure 1-1. Block Diagram25Figure 1-2. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Assignments (64-QFP-1420F)26Figure 1-3. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Assignments (64-LQFP-1010)27Figure 1-4. Pin Circuit Type A30Figure 1-5. Pin Circuit Type B (nRESET)30Figure 1-6. Pin Circuit Type E-4 (P0, P1)30Figure 1-7. Pin Circuit Type H-431Figure 1-8. Pin Circuit Type H-8 (P2.1 P2.7, P3)31Figure 1-9. Pin Circuit Type H-9 (P4, P5, P6)32Figure 1-10. Pin Circuit Type H-10 (P2.0)33Table 1-1. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Descriptions282 ADDRESS SPACES34OVERVIEW34PROGRAM MEMORY (ROM)35SMART OPTION36REGISTER ARCHITECTURE38REGISTER PAGE POINTER (PP)41PROGRAMMING TIP Using the Page Pointer for RAM Clear (Page 0, Page 1)42REGISTER SET 143REGISTER SET 243PRIME REGISTER SPACE44WORKING REGISTERS45USING THE REGISTER POINTS46PROGRAMMING TIP Setting the Register Pointers46PROGRAMMING TIP Using the RPs to Calculate the Sum of a Series of Registers47REGISTER ADDRESSING48COMMON WORKING REGISTER AREA (C0HCFH)50PROGRAMMING TIP Addressing the Common Working Register Area514-BIT WORKING REGISTER ADDRESSING518-BIT WORKING REGISTER ADDRESSING53SYSTEM AND USER STACK55Programming TIP Standard Stack Operations Using PUSH and POP56Figure 2-1. Program Memory Address Space35Figure 2-2. Smart Option36Figure 2-3. Internal Register File Organization (S3C8275X)39Figure 2-4. Internal Register File Organization (S3C8278X/C8274X)40Figure 2-5. Register Page Pointer (PP)41Figure 2-6. Set 1, Set 2, Prime Area Register, and LCD Data Register Map44Figure 2-7. 8-Byte Working Register Areas (Slices)45Figure 2-8. Contiguous 16-Byte Working Register Block46Figure 2-9. Non-Contiguous 16-Byte Working Register Block47Figure 2-10. 16-Bit Register Pair48Figure 2-11. Register File Addressing49Figure 2-12. Common Working Register Area50Figure 2-13. 4-Bit Working Register Addressing52Figure 2-14. 4-Bit Working Register Addressing Example52Figure 2-15. 8-Bit Working Register Addressing53Figure 2-16. 8-Bit Working Register Addressing Example54Figure 2-17. Stack Operations55Table 2-1. S3C8275X Register Type Summary38Table 2-2. S3C8278X/C8274X Register Type Summary383 ADDRESSING MODES57OVERVIEW57REGISTER ADDRESSING MODE (R)58INDIRECT REGISTER ADDRESSING MODE (IR)59INDEXED ADDRESSING MODE (X)63DIRECT ADDRESS MODE (DA)66INDIRECT ADDRESS MODE (IA)68RELATIVE ADDRESS MODE (RA)69IMMEDIATE MODE (IM)70Figure 3-1. Register Addressing58Figure 3-2. Working Register Addressing58Figure 3-3. Indirect Register Addressing to Register File59Figure 3-4. Indirect Register Addressing to Program Memory60Figure 3-5. Indirect Working Register Addressing to Register File61Figure 3-6. Indirect Working Register Addressing to Program or Data Memory62Figure 3-7. Indexed Addressing to Register File63Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset64Figure 3-9. Indexed Addressing to Program or Data Memory65Figure 3-10. Direct Addressing for Load Instructions66Figure 3-11. Direct Addressing for Call and Jump Instructions67Figure 3-12. Indirect Addressing68Figure 3-13. Relative Addressing69Figure 3-14. Immediate Addressing704 CONTROL REGISTERS71BLDCON Battery Level Detector Control Register75BTCON Basic Timer Control Register76CLKCON System Clock Control Register77CLOCON Clock Output Control Register78EXTICONH External Interrupt Control Register (High Byte)79EXTICONL External Interrupt Control Register (Low Byte)80EXTIPND External Interrupt Pending Register81FLAGS System Flags Register82FMCON Flash Memory Control Register83FMSECH Flash Memory Sector Address Register (High Byte)84FMSECL Flash Memory Sector Address Register (Low Byte)84FMUSR Flash Memory User Programming Enable Register85IMR Interrupt Mask Register86IPH Instruction Pointer (High Byte)87IPL Instruction Pointer (Low Byte)87IPR Interrupt Priority Register88IRQ Interrupt Request Register89LCON LCD Control Register90OSCCON Oscillator Control Register91P0CONH Port 0 Control Register (High Byte)92P0CONL Port 0 Control Register (Low Byte)93P0PUR Port 0 Pull-Up Control Register94P1CONH Port 1 Control Register (High Byte)95P1CONL Port 1 Control Register (Low Byte)96P1PUR Port 1 Pull-up Control Register97P2CONH Port 2 Control Register (High Byte)98P2CONL Port 2 Control Register (Low Byte)99P2PUR Port 2 Pull-up Control Register100P3CONH Port 3 Control Register (High Byte)101P3CONL Port 3 Control Register (Low Byte)102P3PUR Port 3 Pull-up Control Register103P4CONH Port 4 Control Register (High Byte)104P4CONL Port 4 Control Register (Low Byte)105P5CONH Port 5 Control Register (High Byte)106P5CONL Port 5 Control Register (Low Byte)107P6CON Port 6 Control Register108PP Register Page Pointer109RP0 Register Pointer 0110RP1 Register Pointer 1110SIOCON SIO Control Register111SPH Stack Pointer (High Byte)112SPL Stack Pointer (Low Byte)112STPCON Stop Control Register113SYM System Mode Register114TACON Timer 1/A Control Register115TBCON Timer B Control Register116WTCON Watch Timer Control Register117Figure 4-1. Register Description Format74Table 4-1. Set 1 Registers71Table 4-2. Set 1, Bank 0 Registers72Table 4-3. Set 1, Bank 1 Registers735 INTERRUPT STRUCTURE118OVERVIEW118INTERRUPT TYPES119S3C8275X/C8278X/C8274X INTERRUPT STRUCTURE120INTERRUPT VECTOR ADDRESSES121ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)123SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS123INTERRUPT PROCESSING CONTROL POINTS124PERIPHERAL INTERRUPT CONTROL REGISTERS125SYSTEM MODE REGISTER (SYM)126INTERRUPT PRIORITY REGISTER (IPR)128INTERRUPT MASK REGISTER (IMR)127INTERRUPT PRIORITY REGISTER (IPR)128INTERRUPT REQUEST REGISTER (IRQ)130INTERRUPT PENDING FUNCTION TYPES131Programming Tip How to clear an interrupt pending bit131INTERRUPT SOURCE POLLING SEQUENCE132INTERRUPT SERVICE ROUTINES132GENERATING INTERRUPT VECTOR ADDRESSES133NESTING OF VECTORED INTERRUPTS133INSTRUCTION POINTER (IP)133FAST INTERRUPT PROCESSING133Figure 5-1. S3C8-Series Interrupt Types119Figure 5-2. S3C8275X/C8278X/C8274X Interrupt Structure120Figure 5-3. ROM Vector Address Area121Figure 5-4. Interrupt Function Diagram124Figure 5-5. System Mode Register (SYM)126Figure 5-6. Interrupt Mask Register (IMR)127Figure 5-7. Interrupt Request Priority Groups128Figure 5-8. Interrupt Priority Register (IPR)129Figure 5-9. Interrupt Request Register (IRQ)130Table 5-1. Interrupt Vectors122Table 5-2. Interrupt Control Register Overview123Table 5-3. Interrupt Source Control and Data Registers1256 INSTRUCTION SET135OVERVIEW135DATA TYPES135REGISTER ADDRESSING135ADDRESSING MODES135FLAGS REGISTER (FLAGS)140FLAG DESCRIPTIONS141INSTRUCTION SET NOTATION142CONDITION CODES146INSTRUCTION DESCRIPTIONS147Figure 6-1. System Flags Register (FLAGS)140Table 6-1. Instruction Group Summary136Table 6-2. Flag Notation Conventions142Table 6-3. Instruction Set Symbols142Table 6-4. Instruction Notation Conventions143Table 6-5. Opcode Quick Reference144Table 6-6. Condition Codes1467 CLOCK CIRCUIT222OVERVIEW222SYSTEM CLOCK CIRCUIT222MAIN OSCILLATOR CIRCUITS223SUB OSCILLATOR CIRCUITS223CLOCK STATUS DURING POWER-DOWN MODES224SYSTEM CLOCK CONTROL REGISTER (CLKCON)225CLOCK OUTPUT CONTROL REGISTER (CLOCON)226OSCILLATOR CONTROL REGISTER (OSCCON)227SWITCHING THE CPU CLOCK228PROGRAMMING TIP Switching the CPU clock228Figure 7-1. Crystal/Ceramic Oscillator (fx)223Figure 7-2. External Oscillator (fx)223Figure 7-3. RC Oscillator (fx)223Figure 7-4. Crystal Oscillator (fxt)223Figure 7-5. External Oscillator (fxt)223Figure 7-6. System Clock Circuit Diagram224Figure 7-7. System Clock Control Register (CLKCON)225Figure 7-8. Clock Output Control Register (CLOCON)226Figure 7-9. Clock Output Block Diagram226Figure 7-10. Oscillator Control Register (OSCCON)227Figure 7-11. STOP Control Register (STPCON)2298 RESET and POWER-DOWN230SYSTEM RESET230OVERVIEW230NORMAL MODE RESET OPERATION230HARDWARE RESET VALUES231POWER-DOWN MODES234STOP MODE234IDLE MODE235Table 8-1. S3C8275X/C8278X/C8274X Set 1 Register and Values After RESET231Table 8-2. S3C8275X/C8278X/C8274X Set 1, Bank 0 Register Values After RESET232Table 8-3. S3C8275X/C8278X/C8274X Set 1, Bank 1 Register Values After RESET2339 I/O PORTS236OVERVIEW236PORT DATA REGISTERS237PORT 0238PORT 1242PORT 2246PORT 3248PORT 4250PORT 5252PORT 6254Figure 9-1. S3C8275X/C8278X/C8274X I/O Port Data Register Format237Figure 9-2. Port 0 High-Byte Control Register (P0CONH)239Figure 9-3. Port 0 Low-Byte Control Register (P0CONL)239Figure 9-4. Port 0 Pull-up Control Register (P0PUR)240Figure 9-5. External Interrupt Control Register, Low Byte (EXTICONL)240Figure 9-6. External Interrupt Pending Register (EXTIPND)241Figure 9-7. Port 1 High-Byte Control Register (P1CONH)243Figure 9-8. Port 1 Low-Byte Control Register (P1CONL)243Figure 9-9. Port 1 Pull-up Control Register (P1PUR)244Figure 9-10. External Interrupt Control Register, High Byte (EXTICONH)244Figure 9-11. External Interrupt Control Register, Low Byte (EXTICONL)245Figure 9-12. External Interrupt Pending Register (EXTIPND)245Figure 9-13. Port 2 High-byte Control Register (P2CONH)246Figure 9-14. Port 2 Low-byte Control Register (P2CONL)247Figure 9-15. Port 2 Pull-up Control Register (P2PUR)247Figure 9-16. Port 3 High Byte Control Register (P3CONH)248Figure 9-17. Port 3 Low Byte Control Register (P3CONL)249Figure 9-18. Port 3 Pull-up Control Register (P3PUR)249Figure 9-19. Port 4 High-Byte Control Register (P4CONH)250Figure 9-20. Port 4 Low-Byte Control Register (P4CONL)251Figure 9-21. Port 5 High-Byte Control Register (P5CONH)252Figure 9-22. Port 5 Low-Byte Control Register (P5CONL)253Figure 9-23. Port 6 Control Register (P6CON)254Table 9-1. S3C8275X/C8278X/C8274X Port Configuration Overview236Table 9-2. Port Data Register Summary23710 BASIC TIMER255OVERVIEW255BASIC TIMER CONTROL REGISTER (BTCON)256BASIC TIMER FUNCTION DESCRIPTION257Figure 10-1. Basic Timer Control Register (BTCON)256Figure 10-2. Basic Timer Block Diagram25811 TIMER 1259ONE 16-BIT TIMER MODE (TIMER 1)259OVERVIEW259FUNCTION DESCRIPTION259TWO 8-BIT TIMERS MODE (TIMER A and B)262OVERVIEW262FUNCTION DESCRIPTION262Figure 11-1. Timer 1/A Control Register (TACON)260Figure 11-2. Timer 1 Block Diagram (One 16-bit Mode)261Figure 11-3. Timer 1/A Control Register (TACON)263Figure 11-4. Timer B Control Register (TBCON)264Figure 11-5. Timer A Block Diagram (Two 8-bit Timers Mode)265Figure 11-6. Timer B Block Diagram (Two 8-bit Timers Mode)26612 WATCH TIMER267OVERVIEW267WATCH TIMER CONTROL REGISTER (WTCON)268WATCH TIMER CIRCUIT DIASGRAM269Figure 12-1. Watch Timer Control Register (WTCON)268Figure 12-2. Watch Timer Circuit Diagram26913 LCD CONTROLLER/DRIVER270OVERVIEW270LCD CIRCUIT DIAGRAM271LCD RAM ADDRESS AREA272LCD CONTROL REGISTER (LCON)273LCD VOLTAGE DIVIDING RESISTOR274COMMON (COM) SIGNALS275SEGMENT (SEG) SIGNALS275Figure 13-1. LCD Function Diagram270Figure 13-2. LCD Circuit Diagram271Figure 13-3. LCD Display Data RAM Organization272Figure 13-4. LCD Control Register (LCON)273Figure 13-5. Internal Voltage Dividing Resistor Connection274Figure 13-6. Select/No-Select Signals in Static Display Mode275Figure 13-7. Select/No-Select Signal in 1/2 Duty, 1/2 Bias Display Mode276Figure 13-8. Select/No-Select Signal in 1/3 Duty, 1/3 Bias Display Mode276Figure 13-9. LCD Signals and Wave Forms Example in 1/4 Duty, 1/3 Bias Display Mode27714 SERIAL I/O INTERFACE278OVERVIEW278PROGRAMMING PROCEDURE278SIO CONTROL REGISTERS (SIOCON)279SIO PRE-SCALER REGISTER (SIOPS)280SIO BLOCK DIAGRAM280SERIAL I/O TIMING DIAGRAM (SIO)281Figure 14-1. Serial I/O Module Control Register (SIOCON)279Figure 14-2. SIO Prescaler Register (SIOPS)280Figure 14-3. SIO Functional Block Diagram280Figure 14-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)281Figure 14-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)28115 BATTERY LEVEL DETECTOR282OVERVIEW282BATTERY LEVEL DETECTOR CONTROL REGISTER (BLDCON)283Figure 15-1. Block Diagram for Voltage Level Detect282Figure 15-2. Battery Level Detect Circuit and Control Register283Table 15-1. BLDCON Value and Detection Level28316 EMBEDDED FLASH MEMORY INTERFACE284OVERVIEW284USER PROGRAM MODE285FLASH MEMORY CONTROL REGISTERS (USER PROGRAM MODE)285ISPTM (ON-BOARD PROGRAMMING) SECTOR288SECTOR ERASE290PROGRAMMING TIP Sector Erase291PROGRAMMING292PROGRAMMING TIP Program293READING294PROGRAMMING TIP Reading294HARD LOCK PROTECTION295PROGRAMMING TIP Hard Lock Protection295Figure 16-1. Flash Memory Control Register (FMCON)285Figure 16-2. Flash Memory User Programming Enable Register (FMUSR)286Figure 16-3. Flash Memory Sector Address Register, High Byte (FMSECH)287Figure 16-4. Flash Memory Sector Address Register, Low Byte (FMSECL)287Figure 16-5. Program Memory Address Space288Figure 16-6. Sector Configurations in User Program Mode290Table 16-1. ISP Sector Size289Table 16-2. Reset Vector Address28917 ELECTRICAL DATA296Figure 17-1. Stop Mode Release Timing When Initiated by an External Interrupt300Figure 17-2. Stop Mode Release Timing When Initiated by a RESET301Figure 17-3. Input Timing for External Interrupts302Figure 17-4. Input Timing for RESET303Figure 17-5. Serial Data Transfer Timing303Figure 17-6. LVR (Low Voltage Reset) Timing304Figure 17-7. Clock Timing Measurement at XIN306Figure 17-8. Clock Timing Measurement at XTIN307Figure 17-9. Operating Voltage Range308Table 17-1. Absolute Maximum Ratings297Table 17-2. D.C. Electrical Characteristics297Table 17-3. Data Retention Supply Voltage in Stop Mode300Table 17-4. Input/Output Capacitance301Table 17-5. A.C. Electrical Characteristics302Table 17-6. Battery Level Detector Electrical Characteristics304Table 17-7. LVR (Low Voltage Reset) Electrical Characteristics304Table 17-8. Main Oscillation Characteristics305Table 17-9. Sub Oscillation Characteristics305Table 17-10. Main Oscillation Stabilization Time306Table 17-11. Sub Oscillation Stabilization Time307Table 17-12. A.C. Electrical Characteristics for Internal Flash ROM30818 MECHANICAL DATA309Figure 18-1. 64-Pin QFP Package Dimensions (64-QFP-1420F)309Figure 18-2. 64-Pin LQFP Package Dimensions (64-LQFP-1010)31019 S3F8275X/F8278X/F8274X FLASH MCU311OVERVIEW311OPERATING MODE CHARACTERISTICS315Figure 19-1. S3F8275X/F8278X/F8274X Pin Assignments (64-QFP-1420F)312Figure 19-2. S3F8275X/F8278X/F8274X Pin Assignments (64-LQFP-1010)313Figure 19-3. Operating Voltage Range317Table 19-1. Descriptions of Pins Used to Read/Write the Flash ROM314Table 19-2. Comparison of S3F8275X/F8278X/F8274X and S3C8275X/C8278X/C8274X Features314Table 19-3. Operating Mode Selection Criteria315Table 19-4. D.C. Electrical Characteristics31620 DEVELOPMENT TOOLS318OVERVIEW318SHINE318SAMA ASSEMBLER318SASM88318HEX2ROM318TARGET BOARDS318TB8275/8/4 TARGET BOARD320SMDS2+ SELECTION (SAM8)323IDLE LED323STOP LED323Figure 20-1. SMDS Product Configuration (SMDS2+)319Figure 20-2. TB8275/8/4 Target Board Configuration320Figure 20-3. 40-Pin Connectors (J101, J102) for TB8275/8/4324Figure 20-4. S3E8270 Cables for 64-QFP Package324Table 20-1. Power Selection Settings for TB8275/8/4321Table 20-2. Main-clock Selection Settings for TB8275/8/4321Table 20-3. Select Smart Option Source Setting for TB8275/8/4322Table 20-4. Smart Option Switch Settings for TB8275/8/4322Table 20-5. Device Selection Settings for TB8275/8/4323Table 20-6. The SMDS2+ Tool Selection Setting323Größe: 2,55 MBSeiten: 324Language: EnglishHandbuch öffnen