Benutzerhandbuch für Samsung MZMPC128HBFU-00000

Inhaltsverzeichnis

• 1.0 General Description

  5
• 2.0 Mechanical Specification

  6
  • 2.1 Physical dimensions and Weight

    6
• 3.0 Product Specifications

  7
  • 3.1 System Interface and Configuration

    7
  • 3.2 System Performance

    7
  • 3.3 Drive Capacity

    7
  • 3.4 Supply Voltage

    7
  • 3.5 System Power Consumption

    7
  • 3.6 System Reliability

    8
  • 3.7 Environmental Specifications

    8
• 4.0 Electrical Interface Specification

  8
  • 4.1 Serial ATA Interface connector

    8
  • 4.2 Pin Assignments

    9
• 5.0 Frame Information Structure (FIS)

  10
  • 5.1 Register - Host to Device

    10
  • 5.2 Register - Device to Host

    11
  • 5.3 Data

    12
  • 5.4 PIO Setup

    12
  • 5.5 DMA Activate - Device to Host

    13
  • 5.6 DMA Setup

    13
  • 5.7 Set Device Bits - Device to Host

    13
• 6.0 Shadow Register Block registers Description

  14
  • 6.1 Command Register

    14
  • 6.2 Device Control Register

    14
    • 6.2.1 Field / bit description

      14
  • 6.3 Device / Head Register

    14
    • 6.3.1 Field / bit description

      14
  • 6.4 Error Register

    14
    • 6.4.1 Field / bit description

      14
  • 6.5 Features Register

    15
  • 6.6 Cylinder High (LBA High) Register

    15
  • 6.7 Cylinder Low (LBA Mid) Register

    15
  • 6.8 Sector Number (LBA low) Register

    15
  • 6.9 Sector Count Register

    15
  • 6.10 Status Register

    15
    • 6.10.1 Field / bit description

      15
• 7.0 Command Descriptions

  16
  • 7.1 Supported ATA Commands

    16
  • 7.2 SECURITY FEATURE Set

    17
    • 7.2.1 SECURITY mode default setting

      17
    • 7.2.2 Initial setting of the user password

      17
    • 7.2.3 SECURITY mode operation from power-on

      17
    • 7.2.4 Password lost

      17
  • 7.3 SMART FEATURE Set (B0h)

    17
    • 7.3.1 Sub Command

      17
      • 7.3.1.1 S.M.A.R.T. Read Attribute Values (subcommand D0h)

        17
      • 7.3.1.2 S.M.A.R.T. Read Attribute Thresholds (subcommand D1h)

        18
      • 7.3.1.3 S.M.A.R.T. Enable/Disable Attribute Autosave (subcommand D2h)

        18
      • 7.3.1.4 S.M.A.R.T. Save Attribute Values (subcommand D3h)

        18
      • 7.3.1.5 S.M.A.R.T. Execute Off-line Immediate (subcommand D4h)

        18
      • 7.3.1.6 S.M.A.R.T. Selective self-test routine

        19
      • 7.3.1.7 S.M.A.R.T. Read Log Sector (subcommand D5h)

        20
      • 7.3.1.8 S.M.A.R.T. Write Log Sector (subcommand D6h)

        20
      • 7.3.1.9 S.M.A.R.T. Enable Operations (subcommand D8h)

        20
      • 7.3.1.10 S.M.A.R.T. Disable Operations (subcommand D9h)

        20
      • 7.3.1.11 S.M.A.R.T. Return Status (subcommand DAh)

        21
      • 7.3.1.12 S.M.A.R.T. Enable/Disable Automatic Off-line (subcommand DBh)

        21
    • 7.3.2 Device Attribute Data Structure

      22
      • 7.3.2.1 Data Structure Revision Number

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      • 7.3.2.2 Individual Attribute Data Structure

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      • 7.3.2.3 Off-Line Data Collection Status

        24
      • 7.3.2.4 Self-test execution status

        24
      • 7.3.2.5 Total time in seconds to complete off-line data collection activity

        24
      • 7.3.2.6 Current segment pointer

        24
      • 7.3.2.7 Off-line data collection capability

        24
      • 7.3.2.8 S.M.A.R.T. Capability

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      • 7.3.2.9 Error logging capability

        25
      • 7.3.2.10 Self-test failure check point

        25
      • 7.3.2.11 Self-test completion time

        25
      • 7.3.2.12 Data Structure Checksum

        25
    • 7.3.3 Device Attribute Thresholds data structure

      25
      • 7.3.3.1 Data Structure Revision Number

        25
      • 7.3.3.2 Individual Thresholds Data Structure

        26
      • 7.3.3.3 Attribute ID Numbers

        26
      • 7.3.3.4 Attribute Threshold

        26
      • 7.3.3.5 Data Structure Checksum

        26
    • 7.3.4 S.M.A.R.T. Log Directory

      26
    • 7.3.5 S.M.A.R.T. error log sector

      27
      • 7.3.5.1 S.M.A.R.T. error log version

        27
      • 7.3.5.2 Error log pointer

        27
      • 7.3.5.3 Device error count

        27
      • 7.3.5.4 Error log data structure

        27
      • 7.3.5.5 Command data structure

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      • 7.3.5.6 Error data structure

        29
    • 7.3.6 Self-test log structure

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    • 7.3.7 Selective self-test log data structure

      30
    • 7.3.8 Error reporting

      31
• 8.0 OOB signaling and Phy Power State

  31
  • 8.1 OOB signaling

    31
    • 8.1.1 OOB signal spacing

      31
  • 8.2 Phy Power State

    32
    • 8.2.1 COMRESET sequence state diagram

      32
    • 8.2.2 Interface Power States

      32
      • 8.2.2.1 PHYRDY

        32
      • 8.2.2.2 Partial

        32
      • 8.2.2.3 Slumber

        32
    • 8.2.3 Partial/Slumber to PHYRDY

      32
      • 8.2.3.1 Host Initiated

        32
      • 8.2.3.2 Device Initiated

        32
    • 8.2.4 PHYRDY to Partial/Slumber

      33
      • 8.2.4.1 Host Initiated for Partial

        33
      • 8.2.4.2 Device Initiated for Partial

        33
• 9.0 SATA II Optional Feature

  34
  • 9.1 Asynchronous Signal Recovery

    34
• 10.0 Identify Device Data

  35
• 11.0 Ordering Information

  37
• 12.0 Product Line up

  37