Hitachi H*/3694F-ZTAT User Manual

Rev. 1.0, 07/01, page 232 of 372

1

AAS

0

R/W

Slave Address Recognition Flag

In slave receive mode, this flag is set to 1 if the first frame
following a start condition matches bits SVA6 to SVA0 in
SAR.

[Setting conditions]

•

  When the slave address is detected in slave receive

mode

•

  When the general call address is detected in slave

receive mode.

 [Clearing condition]

•

  When 0 is written in AAS after reading AAS=1

0

ADZ

0

R/W

General Call Address Recognition Flag

This bit is valid in I

2

C bus format slave receive mode.

[Setting condition]

•

  When the general call address is detected in slave

receive mode

[Clearing conditions]

•

  When 0 is written in ADZ after reading ADZ=1

SAR is an 8-bit readable/writable register that selects the communication format and sets the slave
address. When the chip is in slave mode with the I

2

C bus format, if the upper 7 bits of SAR match

the upper 7 bits of the first frame received after a start condition, the chip operates as the slave
device.

7 to
1

SVA6 to

SVA0

0

R/W

Slave Address 6 to 0

These bits set a unique address in bits SVA6 to SVA0,
differing form the addresses of other slave devices
connected to the I

2

C bus.

0

FS

0

R/W

Format  Select

0: I

2

C bus format is selected.

1: Clocked synchronous serial format is selected.