Silicon Laboratories SI5375 User Manual

The Si5324 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance.
The Si5324 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two independent,
synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides
virtually any frequency translation combination across this operating range. The Si5324 input clock frequency and
clock multiplication ratios are programmable through an I

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C or SPI interface. The DSPLL loop bandwidth is digitally

programmable, providing jitter performance optimization at the application level. The Si5324 features loop
bandwidth values as low as 4 Hz. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5324 is ideal for providing
clock multiplication and jitter attenuation in high-performance timing applications. See "7. Microprocessor
Controlled Parts (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)" on page 76
for a complete description.

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