Mentor v8.6_4 User Manual

FastScan and FlexTest Reference Manual, V8.6_4

Tools Supported: FastScan and FlexTest

Scope: All modes

SET CApture Clock {primary_input_pin | clock_procedure_name} [-Atpg]

Specifies the capture clock name for random pattern simulation.

The Set Capture Clock command performs slightly differently depending on
whether you are using FastScan or FlexTest. In either case, you can use the Report
Environment command to list the capture clock and the Report Clocks command
to identify the current list of clocks.

The following paragraphs describe how the Set Capture Clock command operates
for each tool.

The Set Capture Clock command specifies the name of the capture clock that the
tool uses during random pattern simulation. You can specify the name of a
specific pin in a test procedure file that identifies the pin. The pin must be a
currently defined clock pin. Also, the capture clock that you specify cannot have a
pin constraint.

If you do not specify a capture clock with this command, FastScan sets the capture
clock to none. If there is no capture clock and there is only one clock in the circuit
that is not a set or reset line, FastScan sets that clock as the capture clock during
the rules checking and displays a warning message identifying the capture clock.

The Set Capture Clock command allows the design rules checker to support the
internal scan circuitry within certain boundary scan designs.

For certain boundary scan designs to support their internal scan designs, they only
allow one cycle for each capture. For that one capture cycle, FlexTest must use the
boundary scan clock and all other clocks must be at their off states.