Mentor v8.6_4 User Manual
FastScan and FlexTest Reference Manual, V8.6_4
4-32
FlexTest Test Pattern File Format
Test Pattern File Formats
o
Unknown direction dump character ‘1’ will be used as an input ‘1’ on
an input pin or a measure ‘1’ on an output pin.
an input pin or a measure ‘1’ on an output pin.
o
All other unknown direction dump characters,
‘?’,’F’,’A’,’a’,’B’,’b’,’C’,’c’, and ‘f’, will be used as an input ‘Z’ on an
input pin and a measure ‘X’ on an output pin.
‘?’,’F’,’A’,’a’,’B’,’b’,’C’,’c’, and ‘f’, will be used as an input ‘Z’ on an
input pin and a measure ‘X’ on an output pin.
An Example of Using VCD Reader
Following is an example of using VCD Reader from FlexTest:
Design netlist in Verilog
/*
* DESC: Generated by DFTAdvisor at Tue Mar 11 17:24:02 1997
*/
module test_vcd ( rb , in2 , cnt1 , clk , buf_in , out_ff , out1 , buf_out , ixo );
input rb , in2 , cnt1 , clk , buf_in ;
output out_ff , out1 , buf_out ;
inout ixo ;
wire \N$10 ;
MZTH \I$1 (.IO ( ixo ), .OUT( out1 ) , .C ( cnt1 ) , .IN ( in2 ));
MD20E \I$2 (.NQ ( \N$10 ) , .Q ( out_ff ) , .CK ( clk ) , .D ( \N$10 ) , .R( rb ));
MOPH \I$3 (.OUT ( buf_out ) , .IN ( buf_in ));
endmodule
Verilog Test Bench which generates LSI extension of VCD file in Verilog-
XL:
XL:
//
// Verilog format test patterns produced by FlexTest v8.5_5.6
// Filename : PAT/pat1_verilog
// Timefile : DEFAULT
// Scan operation : PARALLEL
// Fault : STUCK
// Coverage : 77.27(TC) 73.91(FC)
// Date : Fri Jun 6 15:01:50 1997
// Verilog format test patterns produced by FlexTest v8.5_5.6
// Filename : PAT/pat1_verilog
// Timefile : DEFAULT
// Scan operation : PARALLEL
// Fault : STUCK
// Coverage : 77.27(TC) 73.91(FC)
// Date : Fri Jun 6 15:01:50 1997