Epson FX-870/1170 User Manual

The printhead drive circuit receives two types of signals: image data and the pulse length control
signals. Image data is created in the CPU, transferred to the gate array, and latched to the
printhead. The pulse length control signal is set by the CPU. The pulse length is adjusted referring
to the voltage of the 

 V line. These two types of signals are sent to the printhead to print each

dot. Figure 6-29 shows the printhead drive circuit.

The parallel interface circuit controls the data flow from the host computer. When 

 signal

is sent from the host computer, the data is latched into the gate array 

 Data is

transmitted until a BUSY signal is sent back automatically to the host computer to stop the data.
Then, the gate array outputs an 

 signal to 

 (the interrupt signal port) of the CPU. The CPU

then reads the data latched into the gate array and, on completion 

 reading, resets the BUSY

signal to enable the host computer to send more data. Figure 6-30 shows the parallel interface
circuit.