Intel 31244 PCI-X User Manual
33
Intel
®
31244 PCI-X to Serial ATA Controller Interface Ports
5.4
Serial ATA Interface
Four 1.5 Gbits/s Serial ATA ports are located on the GD31244, to support point-to-point
connectivity to disk drives, CDROMs, DVD ROMs or any other Serial ATA target device. Each
port is compliant with the “Serial ATA: High speed Serialized AT Attachment Specification,
Revision 1.0e. High-speed differential duplex serial lines send 8B/10B encoded data to and from
the GD31244 and the target at a maximum raw data rate of 1.2 Gbits/s (150 Mbytes/s). Copies of
the targets Task File Registers are maintained on the GD31244 and transferred as needed to the
target. The Serial ATA protocol is software compatible with all existing operating systems that
support ATA devices, however, performance and reliability are improved since all data is CRC
checked.
connectivity to disk drives, CDROMs, DVD ROMs or any other Serial ATA target device. Each
port is compliant with the “Serial ATA: High speed Serialized AT Attachment Specification,
Revision 1.0e. High-speed differential duplex serial lines send 8B/10B encoded data to and from
the GD31244 and the target at a maximum raw data rate of 1.2 Gbits/s (150 Mbytes/s). Copies of
the targets Task File Registers are maintained on the GD31244 and transferred as needed to the
target. The Serial ATA protocol is software compatible with all existing operating systems that
support ATA devices, however, performance and reliability are improved since all data is CRC
checked.
5.4.1
Direct Port Access (DPA)
The SATA Direct Port Access architecture allows for independent control of the SATA devices.
Unlike ATA master/slave configuration where only one drive may operate at a time, DPA allows
multiple drivers to be accessed concurrently. In addition, each port supports its own DMA channel
allowing each port to transfer data independently (between a device and memory).
Unlike ATA master/slave configuration where only one drive may operate at a time, DPA allows
multiple drivers to be accessed concurrently. In addition, each port supports its own DMA channel
allowing each port to transfer data independently (between a device and memory).
The DPA mode does change the register layout from PCI IDE. Therefore, legacy device drivers do
not support this mode. DPA requires the registers (including the Command Block, Control Block,
DMA, and SATA superset) for each drive is available at all times. Instead of using I/O space, these
registers are mapped to a single 4 KB block. Each port has 512 KB; the remaining 2048 KB are for
the common port registers. The 4 KB block is mapped using one PCI BAR register.
not support this mode. DPA requires the registers (including the Command Block, Control Block,
DMA, and SATA superset) for each drive is available at all times. Instead of using I/O space, these
registers are mapped to a single 4 KB block. Each port has 512 KB; the remaining 2048 KB are for
the common port registers. The 4 KB block is mapped using one PCI BAR register.
5.4.2
Extended Voltage Mode
The SATA voltages were designed primarily for a cable connection to the hard drives. In certain
applications, such as NAS/SAN enclosures, the hard disk drives (HDD) are connected to a
backplane, not a cable (typically in desktop systems). Due to the frequency of the SATA interface,
the backplane creates a significant attenuation of the SATA signals. In an effort to simplify system
designs, the GD31244 offers an extended voltage range to help alleviate this issue. This extended
voltage range allows standard SATA HDD to be used with SATA backplanes.
applications, such as NAS/SAN enclosures, the hard disk drives (HDD) are connected to a
backplane, not a cable (typically in desktop systems). Due to the frequency of the SATA interface,
the backplane creates a significant attenuation of the SATA signals. In an effort to simplify system
designs, the GD31244 offers an extended voltage range to help alleviate this issue. This extended
voltage range allows standard SATA HDD to be used with SATA backplanes.
The firmware may be place into the External Voltage Mode by setting bit 14 in PHY Configuration
Register Address 140H to 1. This forces the firmware to operate with this extended voltage range.
Register Address 140H to 1. This forces the firmware to operate with this extended voltage range.
Table 9.
Normal Voltage Mode
Parameter
Description
Minimum
Maximum
Units
∆V
OUT
TXx output differential peak-to-peak voltage swing
400
600
mVp-p
∆V
IN
RXx input differential peak-to-peak voltage swing
325
600
mVp-p
Table 10.
Extended Voltage Mode
Parameter
Description
Minimum
Maximum
Units
∆V
OUT
TXx output differential peak-to-peak voltage swing
800
2000
mVp-p
∆V
IN
RXx input differential peak-to-peak voltage swing
175
2000
mVp-p