Intel IA-32 User Manual

8-42 Vol. 3A

The vector number for the spurious-interrupt vector is specified in the spurious-interrupt vector
register (see Figure 8-23). The functions of the fields in this register are as follows:

Determines the vector number to be delivered to the processor when
the local APIC generates a spurious vector. 

(Pentium 4 and Intel Xeon processors.) Bits 0 through 7 of the this
field are programmable by software. 

(P6 family and Pentium processors). Bits 4 through 7 of the this field
are programmable by software, and bits 0 through 3 are hardwired to
logical ones. Software writes to bits 0 through 3 have no effect.

Allows software to temporarily enable (1) or disable (0) the local 

APIC (see Section 8.4.3, “Enabling or Disabling the Local APIC”).

Determines if focus processor checking is enabled (0) or disabled (1) 

when using the lowest-priority delivery mode. In Pentium 4 and Intel
Xeon processors, this bit is reserved and should be cleared to 0.

Do not program an LVT or IOAPIC RTE with a spurious vector even if you
set the mask bit. A spurious vector ISR does not do an EOI. If for some
reason an interrupt is generated by an LVT or RTE entry, the bit in the in-
service register will be left set for the spurious vector. This will mask all
interrrupts at the same or lower priority

31

0

Reserved

7

Focus Processor Checking

1

APIC Software Enable/Disable

8

9

10

0: APIC Disabled

1: APIC Enabled

Spurious Vector

2

Address: FEE0 00F0H
Value after reset: 0000 00FFH

0: Enabled

1: Disabled

2. For the P6 family and Pentium processors, bits 0 through 3

of the spurious vector are hardwired to 1.

1. Not supported in Pentium 4 and Intel Xeon processors.