Cypress CY62128E User Manual

Document #: 38-05485 Rev. *F

Page 6 of 12

Figure 1.  Read Cycle 1 (Address Transition Controlled) 

Figure 2.  Read Cycle No. 2 (OE Controlled)

 

]

Figure 3.  Write Cycle No. 1 (WE Controlled) 

[11, 15, 19, 20]

PREVIOUS DATA VALID

DATA VALID

RC

t

AA

t

OHA

t

RC

ADDRESS

DATA OUT

50%

50%

DATA VALID

t

RC

t

ACE

t

DOE

t

LZOE

t

LZCE

t

PU

HIGH IMPEDANCE

t

HZOE

t

HZCE

t

PD

IMPEDANCE

I

CC

I

SB

HIGH 

ADDRESS

CE

DATA OUT

V

CC

SUPPLY

CURRENT

OE

DATA VALID

t

HD

t

SD

t

PWE

t

SA

t

HA

t

AW

t

SCE

t

WC

t

HZOE

ADDRESS

CE

WE

DATA IO

OE

NOTE 21

16. The device is continuously selected. OE, CE

1

 = V

IL

, CE

2

 = V

IH

.

17. WE is HIGH for read cycle.
18. Address valid before or similar to CE

1

 transition LOW and CE

2

 transition HIGH.

19. Data IO is high impedance if OE = V

IH

.

20. If CE

1

 goes HIGH or CE

2

 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.

21. During this period, the IOs are in output state and input signals must not be applied.