Intel 2047285001R User Manual

50 ESM-2850 User’s Manual 
 

 

This section allows you to configure the system based on the specific features of the 

installed chipset. This chipset manages bus speeds and access to system memory 

resources, such as DRAM and the external cache. It also coordinates communications 

between the conventional ISA bus and the PCI bus. It must be stated that these items 

should never need to be altered. The default settings have been chosen because they 

provide the best operating conditions for your system. The only time you might consider 

making any changes would be if you discovered that data was being lost while using your 

system. 

The first chipset settings deal with CPU access to dynamic random access memory 

(DRAM). The default timings have been carefully chosen and should only be altered if data 

is being lost. Such a scenario might well occur if your system had mixed speed DRAM 

chips installed so that greater delays may be required to preserve the integrity of the data 

held in the slower memory chips. 

 

This item allows you to select the DRAM timing value by SPD data or Manual by yourself. 

The choices: Manual, By SPD. 

This item controls the time delay (in clock cycles - CLKs) that passes before the SDRAM 

starts to carry out a read command after receiving it. This also determines the number of 

CLKs for the completion of the first part of a burst transfer. In other words, the lower the 

latency, the faster the transaction.

 

The choices: Auto, 2, 2.5, 3.