SBE HW400c/2 User Manual
HighWire HW400c/2 User Reference Guide Rev 1.0
4.2.16 Device Control Register (DCR)
U
15
B
B
B
B
B
B
The Device Control Register (DCR) is a Read/Write register, which controls the CP
timer enable and three resets.
timer enable and three resets.
The Reset pulse applied to any device must conform to the specifications of that particular device.
Please refer to the applicable device manual for details.
Please refer to the applicable device manual for details.
Table 46. Device Control Register (CSR) Offset Address 0x
it 7
it 6
it 5
it 4
it 3
it 2
Bit 1
Bit 0
Re
C
Re
Re
DO
T8
T
T
served Reserved TREN
served
served
CRST
110L_RS
ETHRS
CTREN
= 0
CPU Tim
CPU Tim
CPU Tim
DOCRST
= 0
De-assert Disk-on-Chip RESET (default state)
= 1
Assert Disk-on-Chip RESET
De-assert T8110L RESET (default state)
De-assert T8110L RESET (default state)
tate)
= 1
Assert Ethernet Switch & PHY RESET (minimum 5us)
4.2.17 CPU Timer Register (CTR)
he CPU Timer Register is a Read-Only register. It is used for measuring CPU
ce. The register value increments once for each tick of the (1.5625 MHz)
PI serial clock, i.e. once every 640 ns.
is enabled by writing a “1” to DCR bit 5 (CTREN, see
Section 4.2.16). Otherwise, it is held to a count value of 0x00 when DCR bit 5 is “0.
Bit 7
B
1
Bit 0
er disabled (default state)
er enabled
er enabled
= 1
T8110L_RST = 0
= 1
Assert T8110L RESET
THRST
= 0
De-assert Ethernet Switch & PHY RESET (default s
E
T
performan
S
performan
S
The CPU Timer Register
Table 47. CPU Timer Register (CTR) Offset Address 0x16
it 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit
CTR7 CTR6 CTR5 CTR4 CTR3 CTR2 CTR1 CTR0
TR[7:0]
= 0x00 –> 0xFF
(when DCR bit 5 = 1)
CTR[7:0]
= 0x00
(when DCR bit 5 = 0)
C
October 10, 2006
Copyright 2006, SBE, Inc.
Page
57