Freescale Semiconductor MPC5200B User Manual

Page of 762
MPC5200B Users Guide, Rev. 1
7-58
Freescale Semiconductor
General Purpose Timers (GPT)
21
Stop_Cont
Stop Continuous—Applies to multiple modes, as follows:
0 = Stop
1 = Continuous
IC  mode
Stop operation—At each IC event, counter is reset.
Continuous operation—counter is not reset at each IC event.
Effect is to create Status count values that are cumulative between Capture events. If the 
special Pulse Mode Capture type is specified, the Stop_Cont bit is not used, operation 
fixed as if it were Stop.
OC  mode
Stop operation—Counter resets and stops at first OC event. Note: Software needs to pass 
through Timer_MS=000 state to restart timer.
Continuous operation—counter resets and continues at each OC event.
Effect to is create back-to-back periodic OC events.
BE AWARE
—In this mode the polarity of Stop_cont is reversed. Also, in Stop Mode, the 
output event falsely retriggers at the expiration of the prescale count.
This means the software has to service and output event prior to the prescale expiring. 
Service is defined as programming mode_sel field to 0, which causes the programmed 
prescale and count values to be reset.
PWM  mode
Bit not used, operation is always Continuous.
CPU Timer mode
Stop operation—On counter expiration, Timer waits until Status bit is cleared by passing 
through Timer_MS=000 state before beginning a new cycle. 
Continuous operation—On counter expiration, Timer resets and immediately begin a new 
cycle. 
Effect is to generate fixed periodic timeouts.
WatchDog Timer and GPIO modes
Bit not used.
22
Open_Drn
Open Drain
0 = Normal I/O
1 = Open Drain emulation—affects all modes that drive the I/O pin (GPIO, OC, & PWM). 
Any output “1” is converted to a tri-state at the I/O pin.
23
IntEn
Enable interrupt—enables interrupt generation to the CPU for all modes (IC, OC, PWM, and 
Internal Timer). IntEn is not required for watchdog expiration to create a reset. 1 = enabled
24:25
Reserved
26:27
GPIO
GPIO mode type. Simple GPIO functionality that can be used simultaneously with the Internal 
Timer mode. It is not compatible with IC, OC, or PWM modes, since these modes dictate the 
usage of the I/O pin.
0x=Timer enabled as simple GPIO input
10=Timer enabled as simple GPIO output, value=0
11=Timer enabled as simple GPIO output, value=1 (tri-state if Open_Drn=1)
While in GPIO modes, internal timer mode is also available. To prevent undesired timer 
expiration, keep the CE bit low.
Bit
Name
Description