Emerson MVME147 User Manual

The SCSI interface firmware was designed for processor efficiency.  Whenever 
the SCSI bus is in a state that does not need monitoring, the firmware releases 
the processor so it may perform other functions such as user tasks and lower 
priority events.  In these cases, an interrupt brings processor control back to 
the firmware.  

A return vector is provided to the SCSI firmware in all cases through the 
packet pointed to by register A2.  Whenever the firmware returns to the user 
through this return vector, it flags whether the processor was brought back to 
the firmware through an external interrupt.  This flagging is done by the RTE 
FLAG bit in the status word stored in the user packet.  If the bit = 1, no RTE is 
to be performed by the user.  If the bit = 0, eventually an RTE is required by the 
user to return the processor to the interrupted task.  

Similarly, whenever the RTE instruction is to be executed, the user must 
restore the registers before executing the RTE.  This restoration of registers is 
mandatory  to properly restore the task that was interrupted.  Upon a return 
through the user vector, address register A3 contains an address of a save area 
where the registers were saved.  If A3 = 0, then no registers were saved (that 
is, no interrupt was taken and the RTE FLAG bit should be a 1).  

Processor control is returned to the user in a variety of ways: 

Intermediate status:

$02 Wait for interrupt (open)
$04 Message received
$06 Command received (TARGET role)

or Final status.

Refer to the Interface Rules for a Single Caller section in Chapter 5 for details.  

For the intermediate statuses, control is given back to the firmware in two 
ways.  One is through an WD33C93 interrupt (WAIT FOR INTERRUPT 
(OPEN)).  The other return mechanism is through a direct branch or jump into