ARM r1p3 User Manual

ARM DDI 0363E

9-22

ID013010

This section describes the capabilities of the AXI slave interface, and the attributes of its AXI 
port. You must not make any other assumptions about the behavior of the AXI slave port except 
that it conforms to the AMBA AXI Protocol Specification.

•

The AXI slave interface supports merging of data. When handling an AXI burst of data 
less than 64-bits wide, the AXI slave interface attempts to perform the minimum number 
of TCM accesses required to read or write the data. When an ECC error scheme is in use, 
this sometimes reduces the number of read-modify-write sequences that the AXI slave 
must perform.

•

The AXI slave interface does not support:
—

Security Extensions, all accesses are secure, so AxPROT[1] is not used

—

data and instruction transaction signaling, so AxPROT[2] is not used

—

memory type and cacheability, so AxCACHE is not used

—

atomic accesses. The AXI slave accepts locked transactions but makes no use of the 
locking information, that is, AxLOCK.

•

The AXI slave interface has no exclusive access monitor. If there are any exclusive 
accesses, the AXI slave interface responds with an OKAY response.

•

The width of the ID signals for the AXI slave port is 8 bits.
You must avoid building the processor into an AXI system that requires more than 8 bits 
of ID. The number of bits of ID required by a system can often be reduced by compressing 
the encoding to remove unused values. The AXI master port does not use all possible 
values. See Identifiers for AXI bus accesses on page 9-4 for details.

Table 9-25 shows the AXI slave port attributes.

Combined acceptance capability

7

-

Write interleave depth

1

All write data must be presented to the AXI slave interface in order

Read data reorder depth

1

The AXI slave interface returns all read data in order, even if the bursts 
have different IDs