Lucent Technologies MN102F75K User Manual

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All registers in I

2

C blook cannot be written by byte (by word only). Read by byte 

is possible.

I2CDTRM: I

2

C Transmission Data Register

SCL is held low during interrupt 

servicing, and is cleared high by 

a write to I2CDTRM.

STA: I

2

C start control

STO: I

2

C stop control

Writing to the STA and STO bits allows you to change the state of the 
transmission or reception operation. Table 13-6 shows the settings for dif-

ferent start and stop conditions.

ACK: Acknowledge signal output control

The acknowledge signal is output after every byte transfer, on the ninth 
clock pulse. ACK is normally 1 and transitions to 0 to output an acknowl-

edge (for instance if the master or slave receiver has received a data byte).

DT[7:0]: Data to be transmitted

The parallel data in this field is converted to serial data for transmission to 
the I

2

C bus. It is shifted out MSB first to the interface.

Bit:

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

—

—

—

—

—

STA

STO

ACK

DT7

DT6

DT5

DT4

DT3

DT2

DT1

DT0

Reset:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

R/W:

R

R

R

R

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

0

All

NOP

No state change

1

1

All

NOP

No state change

1

0

Slave receiver

Start

Change to mode indicated by R/W bit.

R/W = 0: Change to master transmitter
R/W = 1: Change to master receiver

Master transmitter

Repeat start

0

1

Slave receiver

Stop read

Change to slave receiver after stop 

condition.

Master transmitter

Stop write