Lucent Technologies MN102F75K User Manual
Interrupts
Interrupt Setup Examples
Panasonic Semiconductor Development Company
MN102H75K/F75K/85K/F85K LSI User Manual
42
Panasonic
2.2.2
Setting Up a Watchdog Timer Interrupt
The watchdog timer interrupt is
provided for detecting and handling
racing. Normal operation is not
guaranteed if the program returns
after a watchdog interrupt. For
actions requiring returns, use a
timer interrupt.
In this example, a watchdog timer reset occurs. The watchdog timer starts
running after a reset, when the NWDEN flag in the CPU mode register (CPUM)
is enabled (set to 0). When the watchdog timer overflows, a nonmaskable
is enabled (set to 0). When the watchdog timer overflows, a nonmaskable
interrupt occurs. This means that the watchdog timer must be cleared in the main
program.
program.
Enabling watchdog timer interrupts
1.
Enable interrupts by writing a 1 to the interrupt enable flag (IE) in the PSW
and setting the interrupt masking level (IM[2:0]) to 7 (b’111’).
and setting the interrupt masking level (IM[2:0]) to 7 (b’111’).
If WDM[1:0] = 00, a watchdog
interrupt occurs when the watch-
interrupt occurs when the watch-
dog timer counts 2
16
cycles
(5.4613 ms at 4-MHz f
OSC
/12-
MHz f
SYSCLK
). The WDM set-
tings have the following mean-
ings:
00:
2
16
(5.46 ms)
01:
2
4
(1.33 µs)
10:
2
12
(0.34 ms)
11:
2
14
(1.37 ms)
2.
Activate the watchdog timer by clearing the NWDEN bit of the CPUM regis-
ter. Set the time limit for the racing detection function in the WDM[1:0]
ter. Set the time limit for the racing detection function in the WDM[1:0]
field.
CPUM (example)
x’00FC00’
■
Clearing the watchdog timer
The main program normally
clears the watchdog timer prior
clears the watchdog timer prior
to a watchdog interrupt.
3.
Set the NWDEN bit in CPUM to 1, then immediately reset it to 0. The
watchdog timer clears to 0 when NWDEN is 1.
watchdog timer clears to 0 when NWDEN is 1.
Figure 2-6 Block Diagram of Watchdog Timer Interrupt
P0
P5
P2
P1
P3
CORE
Interrupts
Timers 0-5
ROM, RAM
Bus Controller
Serial I/Fs
ADC
■
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NW
DEN
WDM
1
WDM
0
—
—
—
—
—
—
—
—
OSC
ID
STOP HALT OSC1
OSC0
Setting:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0