Clevo D900F User Manual
Schematic Diagrams
B - 48 Power Sequence Diagram
B.Schematic Diagrams
Power Sequence Diagram
Sheet 47 of 47
Power Sequence
Diagram
VCORE_ON
Devices
PWR_SW#
DD_ON
SUSB#
Bloomfield
12
0.75VS
1.5V
3
5b
4a
SUSB#
3
PLTRST#(VCCPWRGD)
LTC3850
Tylersberg
VR
SOUTH BRIDGE
NORTH BRIDGE
VRM_PWRGD->ICH_VRM_PWRGD
1
DRAM VR
H_CPURST#
3V
RSMRST#
PWR_BTN#
Clock Generator
H_PWRGD
SC486
P CI
ICH10R
5V
5b
2
14
VDD3/VDD5
SUSC#
P latf orm
PWROKICH
Other
16
5a
Processor
Devi ces
CK_PWRGD
3
PCIRST#
IOH_CLPWROK
CV193
IOH_CLPWROK
14
4b
12-1
11
VCORE VR
NCP5392MNR2G
EC
ITE8512E
DD_ON
DELAY
75 ms
VRM_PWRGD
VCORE
10
6
1.1VS
SC412A
1.1V EN
MOSFET
D900F V0.0 BOOT BLOCK DIAGRAM
3.3VS
6
5VS
6
6
1.8VS
6
Oth er
Power Bottom
6
1.5VS
LP2951CDR2G
3
12V
ISL6314CR
CPU_VTT
VTT_PWRGD
VTT_PWRGD
PM_PWROK
G690L293T73
3VS
(NEW Car d)
PLTRST#
Delay 2ms
PLTRST_DLY#(CORERST#)
H_PWRGD_IOH(COREPWRGOOD)
PLLDET_3V(COREPLLPWRDET)
ICH_VRM_PWRGD
2N3904
PLLDET_3V(COREPLLPWRDET)
H_PWRGD_IOH(COREPWRGOOD)
Follow Design Guide
M XM3. 0
MXM_PWR_EN
MXM_PWR_EN
MXM_PRESNT#
MXM_PRESNT#
MXM_PRESNT#
PLTRST_DLY#(CORERST#)
Delay
6
8
8
9
9
11
11
7a
7b
11
14
15
13-1
13-3
13-2
7b
11
7a
7b
13-1
13-3
15
IOH_CSI_RST
17