ARM NIC-301 User Manual

ARM DDI 0397G

3-4

ID031010

The type defines the number of register blocks in a single AMBA Network Interconnect 
configuration. Table 3-1, Table 3-2 on page 3-5, and Table 3-3 on page 3-6 show the register 
block sub-types for each of the main types.

Table 3-4 on page 3-7 shows the address region control registers and Table 3-5 on page 3-8 
shows the peripheral ID registers.

 In Table 3-1 to Table 3-5 on page 3-8, reserved means:
•

read as zeros

•

writes are ignored.

AHB only means that this register is interpreted as reserved if the interface is not AHB.

Table 3-1 shows the registers that exist for each ASIB.

0x000

-

-

-

-

Reserved.

0x004

-

-

-

-

Reserved.

0x008

-

-

-

-

Reserved.

0x00C

-

-

-

-

Reserved.

0x020

RW

3

4

sync_mode

This register is only present if you configure the block as a 
programmable FIFO. You can configure the register bits as follows:
0 

sync 1:1.

sync n:1.

sync 1:n.

sync m:n.

async.

reserved.

reserved.

reserved.

0x024

RW

1

0

fn_mod2

Bypass merge. This register is only present if upsizing or downsizing, see 
Upsizing data width function on page 2-12, Downsizing data width 
function on page 2-14, and Bypass merge on page 2-13.

0x028

RW

3

0

fn_mod_ahb

This register is valid for AHB interfaces only. You can configure the 
register bits as follows:
0 

rd_incr_override.

wr_incr_override

.

lock_override.

See Lock transactions on page 2-7 for information on overriding locks. 
See Combination 4 on page 2-6 for information on 

wr_incr_override

 and 

rd_incr_override

.

0x02C

 - 

0x03C

-

-

-

-

Reserved.

0x040

RW

4

a

wr_tidemark

Valid only with a FIFO for the WFIFO channel, and if not an AHB slave 
interface. See FIFO and clocking function on page 2-15 for information 
on 

wr_tidemark

.