SMSC LAN1198 User Manual
LAN9118 Family Programmer Reference Guide
SMSC AN 12.12
19
Revision 1.0 (12-14-09)
APPLICATION NOTE
5.6 PHY Detection and Initialization
Applications commonly delegate link set-up to the physical media device (PHY). At initialization, the
driver can direct the PHY to determine the link parameters by auto-negotiating with its link partner (the
link partner is the node on the other side of the Ethernet cable). Using auto-negotiation, the PHY and
its link partner determine the optimum speed (10 or 100 Mbps) and duplex setting (full or half) by
advertising their capabilities to each other, and then choosing the highest capability that both share in
common. Auto-negotiation is documented in the 802.3u Fast Ethernet supplement to the IEEE
specification.
driver can direct the PHY to determine the link parameters by auto-negotiating with its link partner (the
link partner is the node on the other side of the Ethernet cable). Using auto-negotiation, the PHY and
its link partner determine the optimum speed (10 or 100 Mbps) and duplex setting (full or half) by
advertising their capabilities to each other, and then choosing the highest capability that both share in
common. Auto-negotiation is documented in the 802.3u Fast Ethernet supplement to the IEEE
specification.
Every LAN9118 Family device provides a Media Independent Interface (MII) which connects its internal
MAC to an internal PHY. Each PHY must have a unique 5-bit PHY Address; the internal PHY has a
PHY Address of 00001b, and this address must be used when addressing the internal PHY. Individual
registers within the PHY are indicated through an Index Field. The
MAC to an internal PHY. Each PHY must have a unique 5-bit PHY Address; the internal PHY has a
PHY Address of 00001b, and this address must be used when addressing the internal PHY. Individual
registers within the PHY are indicated through an Index Field. The
below show
how the MAC_CSR_CMD register is used to access the PHY.
The LAN9117 and LAN9115 provide an external MII interface to support an external PHY, for
applications interfacing to other media, such as Fiber, or HPNA. The MII_ACC: PHY Address field
(bits 15:11) must always correctly reflect the active PHY. If an external PHY is used, it must have a
PHY address other than 00000b, 00001b, or 11111b.
applications interfacing to other media, such as Fiber, or HPNA. The MII_ACC: PHY Address field
(bits 15:11) must always correctly reflect the active PHY. If an external PHY is used, it must have a
PHY address other than 00000b, 00001b, or 11111b.
Applications which only operate within a fixed environment might consider hardware strapping options
instead of auto-negotiating. The SPEED_SEL pin can be used to force the speed setting of the PHY
at reset. When the 100 Mbit option is strapped, the PHY will determine whether its link partner is
capable of auto-negotiation. If the link partner is capable of auto-negotiation, then the PHY will
advertise 100Mbps full and half-duplex capabilities, and use the auto-negotiation process to determine
whether the link is full or half-duplex. If the partner is incapable of auto-negotiation, then the PHY will
default to a 100Mbps, half-duplex mode of operation. When the 10 Mbit option is strapped, auto-
negotiation is disabled, and the PHY defaults to a 10Mbps, half-duplex mode of operation. Software
can always override the strap options.
instead of auto-negotiating. The SPEED_SEL pin can be used to force the speed setting of the PHY
at reset. When the 100 Mbit option is strapped, the PHY will determine whether its link partner is
capable of auto-negotiation. If the link partner is capable of auto-negotiation, then the PHY will
advertise 100Mbps full and half-duplex capabilities, and use the auto-negotiation process to determine
whether the link is full or half-duplex. If the partner is incapable of auto-negotiation, then the PHY will
default to a 100Mbps, half-duplex mode of operation. When the 10 Mbit option is strapped, auto-
negotiation is disabled, and the PHY defaults to a 10Mbps, half-duplex mode of operation. Software
can always override the strap options.
Access to the PHY registers is a bit complex, due to the hierarchical organization of the register set.
Recall that the controller contains three sets of registers; the slave set, which are directly accessible
to the host processor, the MAC set, which are indirectly accessible to the host processor through a
command/data register pair (MAC_CSR_CMD/ MAC_CSR_DATA), and the PHY set, which are
accessed by the host through a command/data pair of MAC registers (MII_ACC/ MII_DATA).
Recall that the controller contains three sets of registers; the slave set, which are directly accessible
to the host processor, the MAC set, which are indirectly accessible to the host processor through a
command/data register pair (MAC_CSR_CMD/ MAC_CSR_DATA), and the PHY set, which are
accessed by the host through a command/data pair of MAC registers (MII_ACC/ MII_DATA).
When using the MAC_CSR_CMD register to access the MAC Registers (which include the MII_ACC
and MII_Data Registers), the R/nW bit selects the data direction for the MAC_CSR_Data Register.
When the R/nW bit is set low, the contents of the MAC_CSR_Data Register will be stored into the
MAC Register specified by the CSR Address field. When the R/nW bit is set high, the contents of the
MAC Register specified by the CSR Address field will be loaded into the MAC_CSR_Data Register.
The operation starts when the driver sets the CSR Busy bit high. The driver should continue polling
the MAC_CSR_Command Register until the CSR Busy bit is low to verify that the operation has
completed. A subsequent operation to a MAC Register should not be started until the first operation
and MII_Data Registers), the R/nW bit selects the data direction for the MAC_CSR_Data Register.
When the R/nW bit is set low, the contents of the MAC_CSR_Data Register will be stored into the
MAC Register specified by the CSR Address field. When the R/nW bit is set high, the contents of the
MAC Register specified by the CSR Address field will be loaded into the MAC_CSR_Data Register.
The operation starts when the driver sets the CSR Busy bit high. The driver should continue polling
the MAC_CSR_Command Register until the CSR Busy bit is low to verify that the operation has
completed. A subsequent operation to a MAC Register should not be started until the first operation
Table 5.3 Using the MAC_CSR_CMD Register to Access the MII_ACC Register
MAC_CSR_CMD (ACCESSING MII_ACC REGISTER)
CSR Busy
R/nW
Reserved (29:8)
CSR Address (7:0)
1
1:0
0x6
Table 5.4 Using the MAC_CSR_CMD Register to Access the MII_DATA Register
MAC_CSR_CMD (ACCESSING MII_DATA REGISTER)
CSR Busy
R/nW
Reserved (29:8)
CSR Address (7:0)
0x7