Nxp Semiconductors UM10310 User Manual
UM10310_1
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 01 — 1 December 2008
105 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
15.3 Watchdog clock source
The watchdog timer system has an on-chip 400 KHz oscillator. The watchdog timer can
be clocked from the watchdog oscillator, PCLK or external crystal oscillator (refer to
be clocked from the watchdog oscillator, PCLK or external crystal oscillator (refer to
) by configuring the WDCLK bit in the Watchdog Control Register WDCON and
XTALWD bit in CLKCON register. When the watchdog feature is enabled, the timer must
be fed regularly by software in order to prevent it from resetting the CPU.
be fed regularly by software in order to prevent it from resetting the CPU.
WDCLK bit is used to switch between watchdog oscillator and PCLK. And XTALWD bit is
used to switch between watchdog oscillator/PCLK and external crystal oscillator. After
changing clock source, switching of the clock source will not immediately take effect. As
shown in
used to switch between watchdog oscillator/PCLK and external crystal oscillator. After
changing clock source, switching of the clock source will not immediately take effect. As
shown in
, the selection is loaded after a watchdog feed sequence. In addition,
due to clock synchronization logic, it can take two old clock cycles before the old clock
source is deselected, and then an additional two new clock cycles before the new clock
source is selected.
source is deselected, and then an additional two new clock cycles before the new clock
source is selected.
Since the prescaler starts counting immediately after a feed, switching clocks can cause
some inaccuracy in the prescaler count. The inaccuracy could be as much as 2 old clock
source counts plus 2 new clock cycles.
some inaccuracy in the prescaler count. The inaccuracy could be as much as 2 old clock
source counts plus 2 new clock cycles.
Note: When switching clocks, it is important that the old clock source is left enabled for
two clock cycles after the feed completes. Otherwise, the watchdog may become disabled
when the old clock source is disabled. For example, suppose PCLK (WCLK = 0) is the
current clock source. After WCLK is set to logic 1, the program should wait at least two
PCLK cycles (4 CCLKs) after the feed completes before going into Power-down mode.
Otherwise, the watchdog could become disabled when CCLK turns off. The watchdog
oscillator will never become selected as the clock source unless CCLK is turned on again
first.
two clock cycles after the feed completes. Otherwise, the watchdog may become disabled
when the old clock source is disabled. For example, suppose PCLK (WCLK = 0) is the
current clock source. After WCLK is set to logic 1, the program should wait at least two
PCLK cycles (4 CCLKs) after the feed completes before going into Power-down mode.
Otherwise, the watchdog could become disabled when CCLK turns off. The watchdog
oscillator will never become selected as the clock source unless CCLK is turned on again
first.
Table 100. Watchdog input clock selection
WDCLK(WDCON.0)
XTALWD(CLKCON.4)
Watchdog input clock
selection
selection
0
0
PCLK
1
0
watchdog oscillator
x
1
External crystal oscillator