Nxp Semiconductors UM10310 User Manual
UM10310_1
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 01 — 1 December 2008
109 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
Bit 2 of AUXR1 is permanently wired as a logic 0. This is so that the DPS bit may be
toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,
without the possibility of inadvertently altering other bits in the register.
toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,
without the possibility of inadvertently altering other bits in the register.
17. Data EEPROM
The P89LPC9321 has 512 bytes of on-chip Data EEPROM that can be used to save
configuration parameters. The Data EEPROM is SFR based, byte readable, byte writable,
and erasable (via row fill and sector fill). The user can read, write, and fill the memory via
three SFRs and one interrupt:
configuration parameters. The Data EEPROM is SFR based, byte readable, byte writable,
and erasable (via row fill and sector fill). The user can read, write, and fill the memory via
three SFRs and one interrupt:
•
Address Register (DEEADR) is used for address bits 7 to 0 (bit 8 is in the DEECON
register).
register).
•
Control Register (DEECON) is used for address bit 8, setup operation mode, and
status flag bit (see
status flag bit (see
•
Data Register (DEEDAT) is used for writing data to, or reading data from, the Data
EEPROM.
EEPROM.
Byte Mode: In this mode data can be read and written to one byte at a time. Data is in the
DEEDAT register and the address is in the DEEADR register. Each write requires
approximately 4 ms to complete. Each read requires three machines after writing the
address to the DEEADR register.
DEEDAT register and the address is in the DEEADR register. Each write requires
approximately 4 ms to complete. Each read requires three machines after writing the
address to the DEEADR register.
Table 103. Data EEPROM control register (DEECON address F1h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
EEIF
HVERR
ECTL1
ECTL0
-
EWERR
1
1
EWERR
0
0
EADR8
Reset
0
0
0
0
0
0
0
0
Table 104. Data EEPROM control register (DEECON address F1h) bit description
Bit Symbol
Description
0
EADR8
Most significant address (bit 8) of the Data EEPROM. EADR7-0 are in DEEADR.
1
EWERR
0
0
Data EEPROM write error flag 0. Set when V
DD
< 2.4V during program or erase
operation to indicate the previous operation may not be correct. Can be cleared by
power on reset, watchdog reset or software write.
power on reset, watchdog reset or software write.
2
EWERR
1
1
Data EEPROM write error flag 1. Set when a program or erase is requested and
V
V
DD
<2.4V. Can be cleared by power on reset, watchdog reset or software write.
3
-
Reserved.
5:4
ECTL1:0 Operation mode selection:
The following modes are selected by ECTL[1:0]:
00 — Byte read / write mode.
01 — Reserved.
10 — Row (64 bytes) fill.
11 — Block fill (512 bytes).
6
HVERR
High voltage error. Indicates a programming voltage error during program or
erase.
erase.
7
EEIF
Data EEPROM interrupt flag. Set when a read or write finishes, reset by software.