Nxp Semiconductors UM10310 User Manual

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UM10310_1
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 01 — 1 December 2008 
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NXP Semiconductors
UM10310
P89LPC9321 User manual
is a logic 0, an internal Write Enable (WE) flag is forced set and writes to the flash memory 
and configuration bytes are enabled. If the Active Write Enable (AWE) bit is a logic 1, then 
the state of the internal WE flag can be controlled by the user. 
The WE flag is SET by writing the Set Write Enable (08H) command to FMCON followed 
by a key value (96H) to FMDATA:
FMCON = 0x08;
FMDATA = 0x96;
The WE flag is CLEARED by writing the Clear Write Enable (0BH) command to FMCON 
followed by a key value (96H) to FMDATA, or by a reset:
FMCON = 0x0B;
FMDATA = 0x96;
The ISP function in this device sets the WE flag prior to calling the IAP routines. The IAP 
function in this device executes a Clear Write Enable command following any write 
operation. If the Write Enable function is active, user code which calls IAP routines will 
need to set the Write Enable flag prior to each IAP write function call.
18.15 Configuration byte protection
In addition to the hardware write enable protection, described above, the ‘configuration 
bytes’ may be separately write protected. These configuration bytes include UCFG1, 
UCFG2, BOOTVEC, and BOOTSTAT. This protection applies to both ISP and IAP modes 
and does not apply to ICP or parallel programmer modes.
If the Configuration Write Protect bit (CWP) in BOOTSTAT.6 is a logic 1, writes to the 
configuration bytes are disabled. If the Configuration Write Protect bit (CWP) is a logic 0, 
writes to the configuration bytes are enabled. The CWP bit is set by programming the 
BOOTSTAT register. This bit is cleared by using the Clear Configuration Protection (CCP) 
command in IAP or ISP.
The Clear Configuration Protection command can be disabled in ISP or IAP mode by 
programming the Disable Clear Configuration Protection bit (DCCP) in BOOTSTAT.7 to a 
logic 1. When DCCP is set, the CCP command may still be used in ICP or parallel 
programming modes. This bit is cleared by writing the Clear Configuration Protection 
(CCP) command in either ICP or parallel programming modes.
18.16 IAP error status
It is not possible to use the Flash memory as the source of program instructions while 
programming or erasing this same Flash memory. During an IAP erase, program, or CRC 
the CPU enters a program-idle state. The CPU will remain in this program-idle state until 
the erase, program, or CRC cycle is completed. These cycles are self timed. When the 
cycle is completed, code execution resumes. If an interrupt occurs during an erase, 
programming or CRC cycle, the erase, programming, or CRC cycle will be aborted so that 
the Flash memory can be used as the source of instructions to service the interrupt. An 
IAP error condition will be flagged by setting the carry flag and status information returned. 
The status information returned is shown in 
. If the application permits interrupts 
during erasing, programming, or CRC cycles, the user code should check the carry flag 
after each erase, programming, or CRC operation to see if an error occurred. If the 
operation was aborted, the user’s code will need to repeat the operation.