Nxp Semiconductors UM10310 User Manual
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UM10310_1
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 01 — 1 December 2008
135 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
21. Tables
[1]
. . . . . . .19
Table 10. Interrupt priority level . . . . . . . . . . . . . . . . . . . .26
Table 11. Summary of interrupts . . . . . . . . . . . . . . . . . . .27
Table 12. Number of I/O pins available . . . . . . . . . . . . . .28
Table 13. Port output configuration settings . . . . . . . . . .29
Table 14. Port output configuration . . . . . . . . . . . . . . . . .32
Table 15. BOD Trip points configuration. . . . . . . . . . . . . .34
Table 16. BOD Reset and BOD Interrupt configuration . .34
Table 17. Power reduction modes . . . . . . . . . . . . . . . . . .35
Table 18. Power Control register (PCON - address 87h) bit
Table 11. Summary of interrupts . . . . . . . . . . . . . . . . . . .27
Table 12. Number of I/O pins available . . . . . . . . . . . . . .28
Table 13. Port output configuration settings . . . . . . . . . .29
Table 14. Port output configuration . . . . . . . . . . . . . . . . .32
Table 15. BOD Trip points configuration. . . . . . . . . . . . . .34
Table 16. BOD Reset and BOD Interrupt configuration . .34
Table 17. Power reduction modes . . . . . . . . . . . . . . . . . .35
Table 18. Power Control register (PCON - address 87h) bit
Table 30. Real-time Clock/System Timer clock sources .45
Table 31. Real-time Clock Control register (RTCCON -
Table 31. Real-time Clock Control register (RTCCON -
Table 41. Event delay counter for input capture . . . . . . . 52
Table 42. Output compare pin behavior. . . . . . . . . . . . . . 54
Table 43. CCU control register 1 (TCR21 - address F9h) bit
Table 42. Output compare pin behavior. . . . . . . . . . . . . . 54
Table 43. CCU control register 1 (TCR21 - address F9h) bit
Table 51. UART SFR addresses . . . . . . . . . . . . . . . . . . . 60
Table 52. UART baud rate generation . . . . . . . . . . . . . . 60
Table 53. Baud Rate Generator Control register (BRGCON
Table 52. UART baud rate generation . . . . . . . . . . . . . . 60
Table 53. Baud Rate Generator Control register (BRGCON
Table 60. FE and RI when SM2 = 1 in Modes 2 and 3 . . 66
Table 61. Slave 0/1 examples . . . . . . . . . . . . . . . . . . . . . 69
Table 62. Slave 0/1/2 examples . . . . . . . . . . . . . . . . . . . 69
Table 63. I
Table 61. Slave 0/1 examples . . . . . . . . . . . . . . . . . . . . . 69
Table 62. Slave 0/1/2 examples . . . . . . . . . . . . . . . . . . . 69
Table 63. I
C data register (I2DAT - address DAh) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
C slave address register (I2ADR - address DBh)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 71
C slave address register (I2ADR - address DBh)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 71
C Control register (I2CON - address D8h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
C Control register (I2CON - address D8h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72