Nxp Semiconductors UM10310 User Manual
UM10310_1
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 01 — 1 December 2008
24 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
2.8 Clock sources switch on the fly
P89LPC9321 can implement clock source switch in any sources of watchdog oscillator,
7/14MHz IRC oscillator, external crystal oscillator and external clock input during code is
running. CLKOK bit in register CLKCON is read only and used to indicate the clock switch
status. When CLKOK is ‘0’, clock switch is processing, not completed. When CLKOK is
‘1’, clock switch is completed. When start new clock source switch, CLKOK is cleared
automatically. Notice that when CLKOK is ‘0’, Writing to CLKCON register is not allowed.
During reset, CLKCON register value comes from UCFG1 and UCFG2. The reset value of
CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL
bit comes from UCFG2.7.
7/14MHz IRC oscillator, external crystal oscillator and external clock input during code is
running. CLKOK bit in register CLKCON is read only and used to indicate the clock switch
status. When CLKOK is ‘0’, clock switch is processing, not completed. When CLKOK is
‘1’, clock switch is completed. When start new clock source switch, CLKOK is cleared
automatically. Notice that when CLKOK is ‘0’, Writing to CLKCON register is not allowed.
During reset, CLKCON register value comes from UCFG1 and UCFG2. The reset value of
CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL
bit comes from UCFG2.7.
Note: The oscillator must be configured in one of the following modes: Low frequency crystal, medium frequency crystal, or high
frequency crystal.
frequency crystal.
(1) A series resistor may be required to limit crystal drive levels. This is especially important for low frequency crystals (see text).
Fig 8.
Block diagram of oscillator control.
÷2
002aae108
RTC
CPU
WDT
DIVM
CCLK
UART
OSCCLK
I
2
C-BUS
PCLK
TIMER 0 AND
TIMER 1
HIGH FREQUENCY
MEDIUM FREQUENCY
LOW FREQUENCY
XTAL1
XTAL2
RC OSCILLATOR
WITH CLOCK DOUBLER
WATCHDOG
OSCILLATOR
(7.3728 MHz/14.7456 MHz
± 1 %)
PCLK
RCCLK
SPI
CCU
32
× PLL
(400 kHz
± 5 %)
Table 7.
Clock control register (CLKCON - address FFDEh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
CLKOK
-
-
XTALWD
CLKDBL
FOSC2
FOSC1
FOSC0
Reset
1
0
0
0
x
x
x
x
Table 8.
Clock control register (CLKCON - address FFDEh) bit description
Bit
Symbol
Description
2:0
FOSC2, FOSC1,
FOSC0
FOSC0
CPU oscillator type selection for clock switch. See
for additional
information. Combinations other than those shown in
are reserved for future
use should not be used.
3
CLKDBL
Clock doubler option for clock switch. When set, doubles the output frequency of the
internal RC oscillator.
internal RC oscillator.
4
XTALWD
external crystal oscillator as the clock source of watchdog timer. When =0, disable
external crystal oscillator as the clock source of watchdog timer.
external crystal oscillator as the clock source of watchdog timer.
6:5
-
reserved
7
CLKOK
Clock switch completed flag. When = 1, clock switch is completed. When =0, clock
switch is processing and writing to register CLKCON is not allowed.
switch is processing and writing to register CLKCON is not allowed.