Nxp Semiconductors UM10310 User Manual

UM10310_1

© NXP B.V. 2008. All rights reserved.

The user is discouraged from writing or reading the timer in asynchronous mode. The 
results may be unpredictable

Interrupts and flags are asynchronous. There will be delay as the event may not 
actually be recognized until some CCLK cycles later (for interrupts and reads)

There are seven independent sources of interrupts in the CCU: timer overflow, captured 
input events on Input Capture blocks A/B, and compare match events on Output Compare 
blocks A through D. One common interrupt vector is used for the CCU service routine and 
interrupts can occur simultaneously in system usage. To resolve this situation, a priority 
encode function of the seven interrupt bits in TIFR2 SFR is implemented (after each bit is 
AND-ed with the corresponding interrupt enable bit in the TICR2 register). The order of 
priority is fixed as follows, from highest to lowest: 

TOIF2

TICF2A

TICF2B

TOCF2A

TOCF2B 

TOCF2C 

TOCF2D

An interrupt service routine for the CCU can be as follows:

1. Read the priority-encoded value from the TISE2 register to determine the interrupt 

source to be handled.

2. After the current (highest priority) event is serviced, write a logic 0 to the 

corresponding interrupt flag bit in the TIFR2 register to clear the flag.

3. Read the TISE2 register. If the priority-encoded interrupt source is ‘000’, all CCU 

interrupts are serviced and a return from interrupt can occur. Otherwise, return to step 

 for the next interrupt.