Nxp Semiconductors UM10310 User Manual
UM10310_1
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 01 — 1 December 2008
71 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
The P89LPC9321 CPU interfaces with the I
2
C-bus through six Special Function Registers
(SFRs): I2CON (I
2
C Control Register), I2DAT (I
2
C Data Register), I2STAT (I
2
C Status
Register), I2ADR (I
2
C Slave Address Register), I2SCLH (SCL Duty Cycle Register High
Byte), and I2SCLL (SCL Duty Cycle Register Low Byte).
11.1 I
2
C data register
I2DAT register contains the data to be transmitted or the data received. The CPU can read
and write to this 8-bit register while it is not in the process of shifting a byte. Thus this
register should only be accessed when the SI bit is set. Data in I2DAT remains stable as
long as the SI bit is set. Data in I2DAT is always shifted from right to left: the first bit to be
transmitted is the MSB (bit 7), and after a byte has been received, the first bit of received
data is located at the MSB of I2DAT.
and write to this 8-bit register while it is not in the process of shifting a byte. Thus this
register should only be accessed when the SI bit is set. Data in I2DAT remains stable as
long as the SI bit is set. Data in I2DAT is always shifted from right to left: the first bit to be
transmitted is the MSB (bit 7), and after a byte has been received, the first bit of received
data is located at the MSB of I2DAT.
11.2 I
2
C slave address register
I2ADR register is readable and writable, and is only used when the I
2
C interface is set to
slave mode. In master mode, this register has no effect. The LSB of I2ADR is general call
bit. When this bit is set, the general call address (00h) is recognized.
bit. When this bit is set, the general call address (00h) is recognized.
Fig 31. I
2
C-bus configuration.
OTHER DEVICE
WITH I
2
C-BUS
INTERFACE
SDA
SCL
Rpu
Rpu
OTHER DEVICE
WITH I
2
C-BUS
INTERFACE
P1.3/SDA
P1.2/SCL
I2C MCU
I
2
C-bus
002aac130
Table 63.
I
2
C data register (I2DAT - address DAh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
I2DAT.7
I2DAT.6
I2DAT.5
I2DAT.4
I2DAT.3
I2DAT.2
I2DAT.1
I2DAT.0
Reset
0
0
0
0
0
0
0
0
Table 64.
I
2
C slave address register (I2ADR - address DBh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
I2ADR.6
I2ADR.5
I2ADR.4
I2ADR.3
I2ADR.2
I2ADR.1
I2ADR.0
GC
Reset
0
0
0
0
0
0
0
0
Table 65.
I
2
C slave address register (I2ADR - address DBh) bit description
Bit Symbol
Description
0
GC
General call bit. When set, the general call address (00H) is recognized,
otherwise it is ignored.
otherwise it is ignored.
1:7
I2ADR1:7 7 bit own slave address. When in master mode, the contents of this register has
no effect.