Nxp Semiconductors UM10237 User Manual

UM10237_2

User manual

Rev. 02 — 19 December 2008

180 of 792

NXP Semiconductors

UM10237

Chapter 9: LPC24XX Pin connect

[1]

Pins P027] and P0[28] are open-drain for I

C0 and GPIO functionality for I

C-bus compliance.

5.3 Pin Function Select register 2 (PINSEL2 - 0xE002 C008)

The PINSEL2 register controls the functions of the pins as per the settings listed in

Table 9–132

. The direction control bit in the IO1DIR register (or the FIO1DIR register if the

enhanced GPIO function is selected for port 1) is effective only when the GPIO function is
selected for a pin. For other functions, direction is controlled automatically.

5.4 Pin Function Select Register 3 (PINSEL3 - 0xE002 C00C)

The PINSEL3 register controls the functions of the pins as per the settings listed in

Table 9–133

. The direction control bit in the IO1DIR register (or the FIO1DIR register if the

enhanced GPIO function is selected for port 1) is effective only when the GPIO function is
selected for a pin. For other functions, direction is controlled automatically.

LCD functions are available in LPC2470/78 only and are selected in

Table 9–145

27:26

P0[29]

GPIO Port 0.29

USB_D+1

Reserved

29:28

P0[30]

GPIO Port 0.30

USB_D

−1

Reserved

31:30

P0[31]

GPIO Port 0.31

USB_D+2

Reserved

Table 131. Pin function select register 1 (PINSEL1 - address 0xE002 C004) bit description

PINSEL1 Pin

name

Function when
00

Function
when 01

Function
when 10

Function
when 11

Reset
value

Table 132. Pin function select register 2 (PINSEL2 - address 0xE002 C008) bit description

PINSEL2 Pin

name

Function when
00

Function when
01

Function
when 10

Function
when 11

Reset
value

1:0

P1[0]

GPIO Port 1.0

ENET_TXD0

Reserved

3:2

P1[1]

GPIO Port 1.1

ENET_TXD1

Reserved

5:4

P1[2]

GPIO Port 1.2

ENET_TXD2

MCICLK

PWM0[1]

7:6

P1[3]

GPIO Port 1.3

ENET_TXD3

MCICMD

PWM0[2]

9:8

P1[4]

GPIO Port 1.4

ENET_TX_EN

Reserved