Nxp Semiconductors UM10237 User Manual

UM10237_2

User manual

Rev. 02 — 19 December 2008

202 of 792

NXP Semiconductors

UM10237

Chapter 10: LPC24XX General Purpose Input/Output (GPIO)

Aside from the 32-bit long and word only accessible FIOCLR register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed in

Table 10–169

, too. Next to providing the same functions as the FIOCLR register, these

additional registers allow easier and faster access to the physical port pins.

6.4 GPIO port Pin value register IOPIN and FIOPIN (IO[0/1]PIN -

0xE002 80[0/1]0 and FIO[0/1/2/3/4]PIN - 0x3FFF C0[1/3/5/7/9]4)

This register provides the value of port pins that are configured to perform only digital
functions. The register will give the logic value of the pin regardless of whether the pin is
configured for input or output, or as GPIO or an alternate digital function. As an example,
a particular port pin may have GPIO input, GPIO output, UART receive, and PWM output
as selectable functions. Any configuration of that pin will allow its current logic state to be
read from the corresponding IOPIN register.

If a pin has an analog function as one of its options, the pin state cannot be read if the
analog configuration is selected. Selecting the pin as an A/D input disconnects the digital
features of the pin. In that case, the pin value read in the IOPIN register is not valid.

Table 169. Fast GPIO port output Clear byte and half-word accessible register description

Generic
Register
name

Description

Reset
value

PORTn Register
Address & Name

FIOxCLR0

Fast GPIO Port x output
Clear register 0. Bit 0 in
FIOxCLR0 register
corresponds to pin Px.0 ... bit
7 to pin Px.7.

8 (byte)
WO

0x00

FIO0CLR0 - 0x3FFF C01C
FIO1CLR0 - 0x3FFF C03C
FIO2CLR0 - 0x3FFF C05C
FIO3CLR0 - 0x3FFF C07C
FIO4CLR0 - 0x3FFF C09C

FIOxCLR1

Fast GPIO Port x output
Clear register 1. Bit 0 in
FIOxCLR1 register
corresponds to pin Px.8 ... bit
7 to pin Px.15.

8 (byte)
WO

0x00

FIO0CLR1 - 0x3FFF C01D
FIO1CLR1 - 0x3FFF C03D
FIO2CLR1 - 0x3FFF C05D
FIO3CLR1 - 0x3FFF C07D
FIO4CLR1 - 0x3FFF C09D

FIOxCLR2

Fast GPIO Port x output
Clear register 2. Bit 0 in
FIOxCLR2 register
corresponds to pin Px.16 ...
bit 7 to pin Px.23.

8 (byte)
WO

0x00

FIO0CLR2 - 0x3FFF C01E
FIO1CLR2 - 0x3FFF C03E
FIO2CLR2 - 0x3FFF C05E
FIO3CLR2 - 0x3FFF C07E
FIO4CLR2 - 0x3FFF C09E

FIOxCLR3

Fast GPIO Port x output
Clear register 3. Bit 0 in
FIOxCLR3 register
corresponds to pin Px.24 ...
bit 7 to pin Px.31.

8 (byte)
WO

0x00

FIO0CLR3 - 0x3FFF C01F
FIO1CLR3 - 0x3FFF C03F
FIO2CLR3 - 0x3FFF C05F
FIO3CLR3 - 0x3FFF C07F
FIO4CLR3 - 0x3FFF C09F

FIOxCLRL

Fast GPIO Port x output
Clear Lower half-word
register. Bit 0 in FIOxCLRL
register corresponds to pin
Px.0 ... bit 15 to pin Px.15.

16 (half-word)
WO

0x0000 FIO0CLRL - 0x3FFF C01C

FIO1CLRL - 0x3FFF C03C
FIO2CLRL - 0x3FFF C05C
FIO3CLRL - 0x3FFF C07C
FIO4CLRL - 0x3FFF C09C

FIOxCLRU Fast GPIO Port x output

Clear Upper half-word
register. Bit 0 in FIOxCLRU
register corresponds to pin
Px.16 ... bit 15 to Px.31.

16 (half-word)
WO

0x0000 FIO0CLRU - 0x3FFF C01E

FIO1CLRU - 0x3FFF C03E
FIO2CLRU - 0x3FFF C05E
FIO3CLRU - 0x3FFF C07E
FIO4CLRU - 0x3FFF C09E