Nxp Semiconductors UM10237 User Manual

UM10237_2

© NXP B.V. 2008. All rights reserved.

 

(1) The active data lines will vary with the type of STN panel (4-bit, 8-bit, color, mono) and with single or dual frames.

(2) The LCD panel clock is selected and scaled by the LCD controller and used to produce LCDCLK.

(3) The duration of the LCDLP signal is controlled by the HSW field in the LCD_TIMH register.

(4) The Polarity of the LCDLP signal is determined by the IHS bit in the LCD_POL register.

pixel clock

(internal)

LCD_TIMH (HSW)

LCDLP 

(line synch

 pulse)

suppressed

during LCDLP

LCD_TIMH (HBP)

16  

×

 LCD_TIMH(PPL) 

+

 1

LCD_TIMH (HFP)

LCDDCLK

(panel clock)

horizontal back porch

(defined in pixel clocks)

horizontal front porch

(defined in pixel clocks)

one horizontal line of LCD data

LCDVD[15:0]

(panel data)

one horizontal line