Nxp Semiconductors UM10237 User Manual
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
534 of 792
NXP Semiconductors
UM10237
Chapter 19: LPC24XX SPI
7.6 SPI Test Status Register (SPTSR - 0xE002 0014)
Note: The bits in this register are intended for functional verification only. This register
should not be used for normal operation.
should not be used for normal operation.
This register is a replication of the SPI status register. The difference between the
registers is that a read of this register will not start the sequence of events required to
clear these status bits. A write to this register will set an interrupt if the write data for the
respective bit is a 1.
registers is that a read of this register will not start the sequence of events required to
clear these status bits. A write to this register will set an interrupt if the write data for the
respective bit is a 1.
7.7 SPI Interrupt Register (S0SPINT - 0xE002 001C)
This register contains the interrupt flag for the SPI0 interface.
8.
Architecture
The block diagram of the SPI solution implemented in SPI0 interface is shown in the
Table 466: SPI Test Control Register (SPTCR - address 0xE002 0010) bit description
Bit
Symbol
Description
Reset Value
0
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
NA
7:1
Test
SPI test mode. When 0, the SPI operates normally. When 1,
SCK will always be on, independent of master mode select, and
data availability setting.
SCK will always be on, independent of master mode select, and
data availability setting.
0
Table 467: SPI Test Status Register (SPTSR - address 0xE002 0014) bit description
Bit
Symbol
Description
Reset Value
2:0
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The value read from a reserved bit is not defined.
NA
3
ABRT
Slave abort.
0
4
MODF
Mode fault.
0
5
ROVR
Read overrun.
0
6
WCOL
Write collision.
0
7
SPIF
SPI transfer complete flag.
0
Table 468: SPI Interrupt Register (S0SPINT - address 0xE002 001C) bit description
Bit Symbol Description
Reset
Value
Value
0
SPI
Interrupt
Flag
Interrupt
Flag
SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared
by writing a 1 to this bit.
by writing a 1 to this bit.
Note:
this bit will be set once when SPIE = 1 and at least one of SPIF and
WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0
Interrupt is enabled in the VIC, SPI based interrupt can be processed by
interrupt handling software.
Interrupt is enabled in the VIC, SPI based interrupt can be processed by
interrupt handling software.
0
7:1 -
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
read from a reserved bit is not defined.
NA