Nxp Semiconductors UM10237 User Manual
UM10237_2
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 02 — 19 December 2008
624 of 792
NXP Semiconductors
UM10237
Chapter 24: LPC24XX Timer0/1/2/3
[1]
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
6.1 Interrupt Register (T[0/1/2/3]IR - 0xE000 4000, 0xE000 8000,
0xE007 0000, 0xE007 4000)
The Interrupt Register consists of four bits for the match interrupts and four bits for the
capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be
high. Otherwise, the bit will be low. Writing a logic one to the corresponding IR bit will reset
the interrupt. Writing a zero has no effect.
capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be
high. Otherwise, the bit will be low. Writing a logic one to the corresponding IR bit will reset
the interrupt. Writing a zero has no effect.
6.2 Timer Control Register (T[0/1/2/3]CR - 0xE000 4004, 0xE000 8004,
0xE007 0004, 0xE007 4004)
The Timer Control Register (TCR) is used to control the operation of the Timer/Counter.
CR0
Capture Register 0. CR0 is loaded with the
value of TC when there is an event on the
CAPn[0] (CAP0[0], CAP1[0], CAP2[0],
CAP3[0]) inputs.
value of TC when there is an event on the
CAPn[0] (CAP0[0], CAP1[0], CAP2[0],
CAP3[0]) inputs.
RO
0
T0CR0 - 0xE000 402C
T1CR0 - 0xE000 802C
T2CR0 - 0xE007 002C
T3CR0 - 0xE007 402C
T1CR0 - 0xE000 802C
T2CR0 - 0xE007 002C
T3CR0 - 0xE007 402C
CR1
Capture Register 1. CR1 is loaded with the
value of TC when there is an event on the
CAPn[1] pins (CAP0[1], CAP1[1], CAP2[1],
CAP3[1]) inputs.
value of TC when there is an event on the
CAPn[1] pins (CAP0[1], CAP1[1], CAP2[1],
CAP3[1]) inputs.
RO
0
T0CR1 - 0xE000 4030
T1CR1 - 0xE000 8030
T2CR1 - 0xE007 0030
T3CR1 - 0xE007 4030
T1CR1 - 0xE000 8030
T2CR1 - 0xE007 0030
T3CR1 - 0xE007 4030
EMR
External Match Register. The EMR controls
the external match pins MATn.0-3
(MAT0.0-3 and MAT1.0-3 respectively).
the external match pins MATn.0-3
(MAT0.0-3 and MAT1.0-3 respectively).
R/W
0
T0EMR - 0xE000 403C
T1EMR - 0xE000 803C
T2EMR - 0xE007 003C
T3EMR - 0xE007 403C
T1EMR - 0xE000 803C
T2EMR - 0xE007 003C
T3EMR - 0xE007 403C
CTCR
Count Control Register. The CTCR selects
between Timer and Counter mode, and in
Counter mode selects the signal and
edge(s) for counting.
between Timer and Counter mode, and in
Counter mode selects the signal and
edge(s) for counting.
R/W
0
T0CTCR -
0xE000 4070
T1CTCR -
0xE000 8070
T2CTCR -
0xE007 0070
T3CTCR -
0xE007 4070
0xE000 4070
T1CTCR -
0xE000 8070
T2CTCR -
0xE007 0070
T3CTCR -
0xE007 4070
Table 546. Summary of timer/counter registers
…continued
Generic
Name
Name
Description
Access Reset
Value
[1]
TIMERn Register/
Name & Address
Name & Address
Table 547: Interrupt Register (T[0/1/2/3]IR - addresses 0xE000 4000, 0xE000 8000,
0xE007 0000, 0xE007 4000) bit description
Bit Symbol
Description
Reset
Value
Value
0
MR0 Interrupt Interrupt flag for match channel 0.
0
1
MR1 Interrupt Interrupt flag for match channel 1.
0
2
MR2 Interrupt Interrupt flag for match channel 2.
0
3
MR3 Interrupt Interrupt flag for match channel 3.
0
4
CR0 Interrupt
Interrupt flag for capture channel 0 event.
0
5
CR1 Interrupt
Interrupt flag for capture channel 1 event.
0
6
CR2 Interrupt
Interrupt flag for capture channel 2 event.
0
7
CR3 Interrupt
Interrupt flag for capture channel 3 event.
0