Jameco Electronics 3000 User Manual
User’s Manual
99
7.10.1 External Interrupts
There are two external interrupts. Each interrupt has 2 input pins that can be used to trig-
ger the interrupt. The inputs have a pulse catcher that can detect rising, falling or either ris-
ing or falling edges.
ger the interrupt. The inputs have a pulse catcher that can detect rising, falling or either ris-
ing or falling edges.
Figure 7-6. External Interrupt Line Logic
The external interrupts take place on a transition of the input, which is programmable for
rising, falling or both edges. The pulse catchers are programmable separately to detect a
rising, falling, or either edge in the input. Each of the interrupt pins has its own catcher
device to catch the edge transition and request the interrupt.
rising, falling or both edges. The pulse catchers are programmable separately to detect a
rising, falling, or either edge in the input. Each of the interrupt pins has its own catcher
device to catch the edge transition and request the interrupt.
When the interrupt takes place, both pulse catchers associated with that interrupt are auto-
matically reset. If both edges are detected before the corresponding interrupt takes place,
because the triggering edges occur nearly simultaneously or because the interrupts are
inhibited by the processor priority, then there will be only one interrupt for the two edges
detected. The interrupt service routine can read the interrupt pins via Parallel Port E and
determine which lines experienced a transition, provided that the transitions are not too
fast. Interrupts can also be generated by setting up the matching port E bit as an output and
toggling the bit.
matically reset. If both edges are detected before the corresponding interrupt takes place,
because the triggering edges occur nearly simultaneously or because the interrupts are
inhibited by the processor priority, then there will be only one interrupt for the two edges
detected. The interrupt service routine can read the interrupt pins via Parallel Port E and
determine which lines experienced a transition, provided that the transitions are not too
fast. Interrupts can also be generated by setting up the matching port E bit as an output and
toggling the bit.
External interrupts are cleared automatically during the processor Interrupt Acknowledge
cycle. The Interrupt Acknowledge cycle will always immediately follow an Instruction
Fetch 1 cycle. This instruction byte is ignored, and will be the first byte fetched upon
returning from the interrupt. Interrupt Acknowledge cycles are always followed by two
memory writes to push the contents of the PC onto the stack. Execution then begins at the
appropriate interrupt vector location.
cycle. The Interrupt Acknowledge cycle will always immediately follow an Instruction
Fetch 1 cycle. This instruction byte is ignored, and will be the first byte fetched upon
returning from the interrupt. Interrupt Acknowledge cycles are always followed by two
memory writes to push the contents of the PC onto the stack. Execution then begins at the
appropriate interrupt vector location.
pulse
catcher
catcher
pulse
catcher
catcher
pulse
catcher
catcher
pulse
catcher
catcher
INT1A [PE1]
INT1B [PE5]
INT0A [PE0]
INT0B [PE4]
#1 interrupt acknowledge
#0 interrupt acknowledge