Jameco Electronics 3000 User Manual
110
Rabbit 3000 Microprocessor
7.14 Quadrature Decoder
The two-channel Quadrature Decoder accepts inputs, via Port F, from two external optical
incremental encoder modules. Each channel of the Quadrature Decoder accepts an in-
phase (I) and a quadrature-phase (Q) signal and provides 8-bit counters to track shaft rota-
tion and provide interrupts when the count goes from 0x00 to 0xFF or from 0xFF to 0x00.
The Quadrature Decoder contains digital filters on the inputs to prevent false counts. The
Quadrature Decoder is clocked by the output of Timer A10.
incremental encoder modules. Each channel of the Quadrature Decoder accepts an in-
phase (I) and a quadrature-phase (Q) signal and provides 8-bit counters to track shaft rota-
tion and provide interrupts when the count goes from 0x00 to 0xFF or from 0xFF to 0x00.
The Quadrature Decoder contains digital filters on the inputs to prevent false counts. The
Quadrature Decoder is clocked by the output of Timer A10.
Each Quadrature Decoder channel accepts inputs from either the upper nibble or lower
nibble of Port F. The I signal is input on an odd-numbered port bit, while the Q signal is
input on an even-numbered port bit. There is also a disable selection, which is guaranteed
not to generate a count increment or decrement on either entering or exiting the disable
state. The operation of the counter as a function of the I and Q inputs is shown below.
nibble of Port F. The I signal is input on an odd-numbered port bit, while the Q signal is
input on an even-numbered port bit. There is also a disable selection, which is guaranteed
not to generate a count increment or decrement on either entering or exiting the disable
state. The operation of the counter as a function of the I and Q inputs is shown below.
The Quadrature decoders are clocked by the output of Timer A10, giving a maximum
clock rate of one-half of the peripheral clock rate. The time constant of Timer A10 must be
fast enough to sample the inputs properly. Both the I and Q inputs go through a digital fil-
ter that rejects pulses shorter than two clock period wide. In addition, the clock rate must
be High enough that transitions on the I and Q inputs are sampled in different clock cycles.
The Input Capture may be used to measure the pulse width on the I inputs because they
come from the odd-numbered port bits. The operation of the digital filter is shown below.
clock rate of one-half of the peripheral clock rate. The time constant of Timer A10 must be
fast enough to sample the inputs properly. Both the I and Q inputs go through a digital fil-
ter that rejects pulses shorter than two clock period wide. In addition, the clock rate must
be High enough that transitions on the I and Q inputs are sampled in different clock cycles.
The Input Capture may be used to measure the pulse width on the I inputs because they
come from the odd-numbered port bits. The operation of the digital filter is shown below.
Register Name
Mnemonic
I/O Address
R/W
Reset
Quad Decode Ctrl/Status Register
QDCSR
0x90
R/W
xxxxxxxx
Quad Decode Control Register
QDCR
0x91
W
00xx0000
Quad Decode Count 1 Register
QDC1R
0x94
R
xxxxxxxx
Quad Decode Count 2 Register
QDC2R
0x96
R
xxxxxxxx
00
01 02 03 04 05 06 07 08 07 06 05 04 03 02 01 00 FF
I input
Q input
Counter
Interrupt