Jameco Electronics 3000 User Manual
258
Rabbit 3000 Microprocessor
19.19 Privileged Instructions
The privileged instructions are described in this section. Privilege means that an interrupt
cannot take place between the privileged instruction and the following instruction.
cannot take place between the privileged instruction and the following instruction.
The three instructions below are privileged.
LD SP,HL ; load the stack pointer
LD SP,IY
LD SP,IX
The instructions to load the stack are privileged so that they can be followed by an instruc-
tion to load the stack segment (SSEG) register without the danger of an interrupt taking
place with and incorrect association between the stack pointer and the stack segment reg-
ister. For example,
tion to load the stack segment (SSEG) register without the danger of an interrupt taking
place with and incorrect association between the stack pointer and the stack segment reg-
ister. For example,
LD SP,HL
IOI LD (STACKSEG),A
The following instructions are privileged.
IPSET 0 ; shift IP left and set priority 00 in bits 1,0
IPSET 1
IPSET 2
IPSET 3
IPRES ; rotate IP right 2 bits, restoring previous priority
POP IP ; pop IP register from stack
The instructions to modify the IP register are privileged so that they can be followed by a
return instructions that is guaranteed to execute before another interrupt takes place. This
avoids the possibility of an ever-growing stack.
return instructions that is guaranteed to execute before another interrupt takes place. This
avoids the possibility of an ever-growing stack.
RETI ; pops IP from stack and then pops return address
The instruction
reti
can be used to set both the return address and the IP in a single
instruction. If preceded by a
LD
XPC
, a complete jump or call to a computed address can
be done with no possible interrupt.
LD A,XPC ; get and set the XPC
LD XPC,A
The instruction
LD
XPC,A
is privileged so that it can be followed by other code setting
interrupt priority or program counter without an intervening interrupt.
BIT B,(HL) ; test a bit in memory
The instruction bit
B,(HL)
is privileged to make it possible to implement a semaphore
without disabling interrupts. The following sequence is used. A bit is a semaphore, and the
first task to set the bit owns the semaphore and has a right to manipulate the resources
associated with the semaphore.
first task to set the bit owns the semaphore and has a right to manipulate the resources
associated with the semaphore.
BIT B,(HL)
SET B,(HL)
JP z,ihaveit
; here I don’t have it
The
SET
instruction has no effect on the flags. Since no interrupt takes place after the
BIT
instruction, if the flag is zero that means that the semaphore was not set when tested by the
bit instruction and that the set instruction has set the semaphore. If an interrupt was
allowed between the
bit instruction and that the set instruction has set the semaphore. If an interrupt was
allowed between the
BIT
and set instructions, another routine could set the semaphore and
two routines could think that they both owned the semaphore.