Jameco Electronics 3000 User Manual
User’s Manual
87
7.5 Chip Select Options for Low Power
Some types of flash memory and RAM consume power whenever the chip select is
enabled even if no signals are changing. The chip select behavior of the Rabbit 3000 can
be modified to reduce unnecessary power consumption when the Rabbit 3000 is running
at a reduced clock speed. The short chip select option can be enabled when the processor
clock is divided (by 4, 6, or 8) so as to run at a lower speed.
enabled even if no signals are changing. The chip select behavior of the Rabbit 3000 can
be modified to reduce unnecessary power consumption when the Rabbit 3000 is running
at a reduced clock speed. The short chip select option can be enabled when the processor
clock is divided (by 4, 6, or 8) so as to run at a lower speed.
The short chip select option is exercised with clock select bits 4:2 of the GCSR register as
shown in Table 7-6. Whether the chip select is normal or short is then determined by
whether bit 4 in the GPSCR register is 0 or 1.
shown in Table 7-6. Whether the chip select is normal or short is then determined by
whether bit 4 in the GPSCR register is 0 or 1.
When the short chip select option is enabled, the chip select delays turning on until the end
of the of the memory cycle when it turns on for the last 2 undivided clocks. If the clock is
divided by 6, the memory read cycle with no wait states would normally be 12 undivided
clocks long. With the short chip select, the chip select is on for only 2/12 clocks for a
memory duty cycle of 1/6. If wait states are added, the duty cycle is reduced even more.
For example, if there is one wait state and the clock is divided by 6, the memory bus cycle
will be 18 undivided clocks long and the duty cycle will be 2/18 = 1/9 with the short chip
select option enabled.
of the of the memory cycle when it turns on for the last 2 undivided clocks. If the clock is
divided by 6, the memory read cycle with no wait states would normally be 12 undivided
clocks long. With the short chip select, the chip select is on for only 2/12 clocks for a
memory duty cycle of 1/6. If wait states are added, the duty cycle is reduced even more.
For example, if there is one wait state and the clock is divided by 6, the memory bus cycle
will be 18 undivided clocks long and the duty cycle will be 2/18 = 1/9 with the short chip
select option enabled.
When the short chip select option is enabled, the interrupt sequence will attempt to write
the return address to the stack if an interrupt takes place immediately after an internal or
an external I/O instruction. The chip select will be suppressed during the write cycle, and
the correct return address will not be stored on the stack. This happens only when an inter-
rupt takes place immediately after an I/O instruction when the short chip select option is
enabled. Therefore, when using the short chip select option, ensure that interrupts are dis-
abled during I/O instructions (or do not use short chip select). Interrupts can be disabled
for a single I/O instruction as shown in the following example.
the return address to the stack if an interrupt takes place immediately after an internal or
an external I/O instruction. The chip select will be suppressed during the write cycle, and
the correct return address will not be stored on the stack. This happens only when an inter-
rupt takes place immediately after an I/O instruction when the short chip select option is
enabled. Therefore, when using the short chip select option, ensure that interrupts are dis-
abled during I/O instructions (or do not use short chip select). Interrupts can be disabled
for a single I/O instruction as shown in the following example.
PUSH IP ; save interrupt state
IPSET 3 ; interrupts off
IOE LD a,(hl) ; typical I/O instruction
POP IP ; reenable interrupts
When the 32.768 kHz clock is used as the main processor clock (sleepy mode) the mem-
ory duty cycle can be reduced by enabling a self-timed chip select mode. When the
32.768 kHz clock is used, the clock period is approximately 32 µs, and a normal memory
read cycle without wait states will be approximately 64 µs. No more than a few hundred
nanoseconds are needed to read the memory. The main oscillator is normally shut down
when operating at 32 kHz, and no faster clock is available to time out a short chip select
cycle. To provide for a low-memory-duty cycle, a chip select and memory read can take
place under control of a delay timer that is on the chip. The cycle starts at the start of the
final 64 µs clock of the memory cycle and can be set to enable chip select for a period in
the range of 70 to 200 ns. The data are clocked in early at the end of the delay-driven
cycle. The chip select duty cycle is very small, about 0.2/128 = 1/600.
ory duty cycle can be reduced by enabling a self-timed chip select mode. When the
32.768 kHz clock is used, the clock period is approximately 32 µs, and a normal memory
read cycle without wait states will be approximately 64 µs. No more than a few hundred
nanoseconds are needed to read the memory. The main oscillator is normally shut down
when operating at 32 kHz, and no faster clock is available to time out a short chip select
cycle. To provide for a low-memory-duty cycle, a chip select and memory read can take
place under control of a delay timer that is on the chip. The cycle starts at the start of the
final 64 µs clock of the memory cycle and can be set to enable chip select for a period in
the range of 70 to 200 ns. The data are clocked in early at the end of the delay-driven
cycle. The chip select duty cycle is very small, about 0.2/128 = 1/600.