Hitachi 9900 User Manual
mirrored images of each other. This is illustrated in Figure 17. Control data is “data about
data,” also called “metadata.” Essentially, control information is handled
“out of band” from the data paths, both through a separate memory area and network.
data,” also called “metadata.” Essentially, control information is handled
“out of band” from the data paths, both through a separate memory area and network.
The CM-HSN is a much simpler network design in that every connection is a
point-to-point connection. Only the Cache-HSN (data paths) uses a switched-fabric
topology for its interconnecting network. The CM-HSN also uses a narrower path and
more of them. Figure 17 shows a close-up view of the CM-HSN’s networking topology.
Referring back to the diagram in Figure 2, Chapter 1, there are two CM-HSN paths
connecting the processors to the control memory. However, the diagram in Figure 16 shows
four paths per processor module. There are up to 64 4-bit paths connecting the processors
to the control memory. The diagram in Figure 2 shows the 4-bit paths combined into their
full 8-bit (plus a parity bit) paths. The zoomed-in view in Figure 17 shows all of the ports
to the control memory in its “split” configuration. Again, control memory is mirrored. This
path topology is used to facilitate this mirrored architecture.
topology for its interconnecting network. The CM-HSN also uses a narrower path and
more of them. Figure 17 shows a close-up view of the CM-HSN’s networking topology.
Referring back to the diagram in Figure 2, Chapter 1, there are two CM-HSN paths
connecting the processors to the control memory. However, the diagram in Figure 16 shows
four paths per processor module. There are up to 64 4-bit paths connecting the processors
to the control memory. The diagram in Figure 2 shows the 4-bit paths combined into their
full 8-bit (plus a parity bit) paths. The zoomed-in view in Figure 17 shows all of the ports
to the control memory in its “split” configuration. Again, control memory is mirrored. This
path topology is used to facilitate this mirrored architecture.
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Hi - St a r A rc h i t e c t u re – An In t e rnal Switched Hi e r a rchical Star Ne t w o rk
Figure 17 – Separate
redundant control
memory handles the
exchange of control
information, such as
status, location, and
configuration of data,
between processors and
cache memory.
redundant control
memory handles the
exchange of control
information, such as
status, location, and
configuration of data,
between processors and
cache memory.