ARM R4F User Manual

ARM DDI 0363E

14-26

ID013010

This section describes the cycle timing behavior for the 

MCR

 and 

MRC

 instructions to CP14, the 

debug coprocessor or CP15, the system control coprocessor.

The precise timing of coprocessor instructions is tightly linked with the behavior of the relevant 
coprocessor. Table 14-21 shows the coprocessor instructions cycle timing behavior. Table 14-21 
shows the best case numbers.

 Some instructions such as cache operations take more cycles.

MCR

6

-

-

MCR <cond>

6

-

Condition code passes

4

-

Condition code fails

MRC

6

6

-

MRC <cond>

6

6

Condition code passes

4

4

Condition code fails