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ARM R4F User Manual
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Contents
ARM DDI 0363E
Copyright © 2009 ARM Limited. All rights reserved.
iv
ID013010
Non-Confidential, Unrestricted Access
2.10
Unaligned and mixed-endian data access support ................................................ 2-28
2.11
Big-endian instruction support ............................................................................... 2-29
Chapter 3
Processor Initialization, Resets, and Clocking
3.1
Initialization .............................................................................................................. 3-2
3.2
Resets ...................................................................................................................... 3-6
3.3
Reset modes ............................................................................................................ 3-7
3.4
Clocking ................................................................................................................... 3-9
Chapter 4
System Control Coprocessor
4.1
About the system control coprocessor ..................................................................... 4-2
4.2
System control coprocessor registers ...................................................................... 4-9
Chapter 5
Prefetch Unit
5.1
About the prefetch unit ............................................................................................. 5-2
5.2
Branch prediction ..................................................................................................... 5-3
5.3
Return stack ............................................................................................................. 5-5
Chapter 6
Events and Performance Monitor
6.1
About the events ...................................................................................................... 6-2
6.2
About the PMU ........................................................................................................ 6-6
6.3
Performance monitoring registers ............................................................................ 6-7
6.4
Event bus interface ................................................................................................ 6-19
Chapter 7
Memory Protection Unit
7.1
About the MPU ........................................................................................................ 7-2
7.2
Memory types .......................................................................................................... 7-7
7.3
Region attributes ...................................................................................................... 7-9
7.4
MPU interaction with memory system ................................................................... 7-11
7.5
MPU faults ............................................................................................................. 7-12
7.6
MPU software-accessible registers ....................................................................... 7-13
Chapter 8
Level One Memory System
8.1
About the L1 memory system .................................................................................. 8-2
8.2
About the error detection and correction schemes .................................................. 8-4
8.3
Fault handling .......................................................................................................... 8-7
8.4
About the TCMs ..................................................................................................... 8-13
8.5
About the caches ................................................................................................... 8-18
8.6
Internal exclusive monitor ...................................................................................... 8-34
8.7
Memory types and L1 memory system behavior ................................................... 8-35
8.8
Error detection events ............................................................................................ 8-36
Chapter 9
Level Two Interface
9.1
About the L2 interface .............................................................................................. 9-2
9.2
AXI master interface ................................................................................................ 9-3
9.3
AXI master interface transfers ................................................................................. 9-7
9.4
AXI slave interface ................................................................................................. 9-20
9.5
Enabling or disabling AXI slave accesses ............................................................. 9-23
9.6
Accessing RAMs using the AXI slave interface ..................................................... 9-24
Chapter 10
Power Control
10.1
About power control ............................................................................................... 10-2
10.2
Power management ............................................................................................... 10-3
Chapter 11
Debug
11.1
Debug systems ...................................................................................................... 11-2
11.2
About the debug unit .............................................................................................. 11-3
11.3
Debug register interface ........................................................................................ 11-5
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