ARM R4F User Manual
Programmer’s Model
ARM DDI 0363E
Copyright © 2009 ARM Limited. All rights reserved.
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2.7
Program status registers
The processor contains one CPSR and five SPSRs for exception handlers to use. The program
status registers:
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status registers:
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hold information about the most recently performed ALU operation
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control the enabling and disabling of interrupts
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set the processor operating mode.
Figure 2-4 shows the bit arrangement in the status registers.
Figure 2-4 Program status register
The following sections explain the meanings of these bits:
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2.7.1
The N, Z, C, and V bits
The N, Z, C, and V bits are the condition code flags. You can optionally set them with arithmetic
and logical operations, and also with
and logical operations, and also with
MSR
instructions and
MRC
instructions to R15. The processor
tests these flags in accordance with an instruction's condition code to determine whether to
execute that instruction.
execute that instruction.
In ARM state, most instructions can execute conditionally on the state of the N, Z, C, and V bits.
The exceptions are:
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The exceptions are:
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BKPT
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CPS
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LDC2
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MCR2
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MCRR2
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MRC2
M[4:0]
T
F
I
A
E
IT[7:2]
GE[3:0]
N
J
Greater than
or equal to
or equal to
Java state bit
Sticky overflow
Overflow
Carry/Borrow/Extend
Zero
Negative/Less than
Mode bits
Thumb state bit
FIQ disable
IRQ disable
Imprecise abort
disable bit
disable bit
Data endianness bit
31 30 29 28 27 26 25 24 23
20 19
16 15
10 9 8 7 6 5 4
0
Z C V Q
IT[1:0]
DNM