Intel IXP42X User Manual

Intel

®

 IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

September 2006

DM

Order Number: 252480-006US

505

Software uses the transmit short packet to indicate that the last byte of a data transfer 

has been sent to the FIFO. This indicates to the UDC that a short packet or zero-sized 

packet is ready to transmit.

Software must not set this bit if a packet of 8 bytes is to be transmitted. When the data 

packet is successfully transmitted, the UDC clears this bit. 

The UDC Endpoint 11 Control Status Register contains six bits that are used to operate 

endpoint 11, a Bulk IN endpoint.

0x C800B038

0x00000001

Universal Serial Bus Device Controller Endpoint 10Control and Status Register

Access: Read/Write

(Reserved)

TSP

(Rs

vd)

FST

SST

TUR

FT

F

TP

C

TFS

X

0

0

0

0

0

0

0

1

31:8

Reserved for future use.

7

TSP

Transmit short packet (read/write 1 to set).
1 = Short packet ready for transmission.

6

(Reserved). Always reads 0.

5

FST

Force STALL (read/write).
1 = Issue STALL handshakes to IN tokens.

4

SST

Sent STALL (read/write 1 to clear).
1 = STALL handshake was sent.

3

TUR

Transmit FIFO underrun (read/write 1 to clear).
1 = Transmit FIFO experienced an underrun. 

2

FTF

Flush Tx FIFO (always read 0/ write a 1 to set).
1 = Flush Contents of TX FIFO.

1

TPC

Transmit packet complete (read/write 1 to clear).
0 = Error/status bits invalid.
1 = Transmit packet has been sent and error/status bits are valid.

0

TFS

Transmit FIFO service (read-only).
0 = Transmit FIFO has no room for new data.
1 = Transmit FIFO has room for 1 complete data packet.