Intel 7xx Servers User Manual

4800-18000

1 - 4

2x4MB / 32MB

4200

4966

550 (9409-M50)

4300-8300

1 - 2

2x4MB / 0MB

4200

5634

520 (9408-M25)

4300

1

2x4MB / 0MB

4200

5633

520 (9407-M15)

Processor 

CPW

CPU 

(2)

  

Range

L2/L3 cache 

(1)

per chip

Chip Speed

MHz

Processor

Feature

Model 

*Note:  1. These models have a dedicated L2 cache per processor core, and share the L3 cache 
                 between two processor cores.

2. The range of the number of processor cores per system.

C.3.2  CPW values for IBM BladeCenter JS12 - IBM i operating system

7100

1.8 of 2

2x4MB / 0 MB

3800

52BF

JS12 (7998-60X)

Processor 

CPW 

(3)

CPUs

(2)

  

L2/L3 cache 

(1)

per chip

Chip Speed

MHz

Processor

Feature

Blade Model 

*Note:  1. These models have a dedicated L2 cache per processor core, and no L3 cache 

2. CPW value is for a 1.8-core partition with shared processors and a 0.2-core VIOS partition
3. The value listed is unconstrained CPW (there is sufficient I/O such that the processor would be

the first constrained resource).  The I/O constrained CPW value for a 12-disk configuration is
approximately 1200 CPW (100 CPW per disk).

C.3.3  CPW values for IBM Power Systems - IBM i operating system

76900

40100

21200

10800

2x4MB / 32MB

4700

7380

570 (9117-MMA)

68600

35500

19200

9650

2x4MB / 32MB

4200

5621/5622

570 (9117-MMA)

57600

30100

16100

8150

2x4MB / 32MB

3500

5620

570 (9117-MMA)

16 cores

8 cores

4 cores

2 cores

L2/L3 cache 

(1)

per chip

Chip Speed

MHz

Processor

Feature

Model 

Processor CPW

*Note:  1. These models have a dedicated L2 cache per processor core, and share the L3 cache 
                 between two processor cores.

C.4.1  IBM i5/OS running on IBM BladeCenter JS22 using POWER6 processor technology

IBM i 6.1 Performance Capabilities Reference - January/April/October 2008

©

 Copyright IBM Corp. 2008